shared data bus within ALU design for FPGA synthesis

Hey there,

I'm attempting to design an ALU with a single 4-bit data line which
supplies operand A, operand B, and the mode opcode to select the
function the ALU should perform.

I'm quite new to the world of HDL and FPGA synthesis.

What I'm trying to do is to use latches to hold the values for opcode
A, opcode and the mode operand so the ALU system's Always statement
looks to the ouput of the register on the end of the latch which will
hold the mode opcode. When this register changes it will then perform
the operation specified by the mode opcode.

Are latches the correct way to do this? I am designing for minimal area
of the fpga and am using a state machine which controls the sequence of
the system.

The whole system will be clocked by a PC's parallel port for
demonstration. The order that the data will appear on the shared 4-bit
bus is: A operand, B operand then the mode opcode.

I'm trying to understand what issues may arise due to inferring
latches. I can't see any other way of doing it so that the opcodes and
the mode operand are held in the correct registers so the ALU can read
them properly.

Any help appreciated, many thanks! AL

 

[michaelst@gmail.com]

I wouldn't recommend you to use latches. Especially in FPGA.
Why FFs are not enough for you? There is no difference in area between
latch and FF for FPGA.

 

Thanks for your reply.

As the data bus is shared I don't want the same data being stored on
the FF's/latches feeding the ALU operands.

In the state machine can I set a FF so it stores the data but by the
next state won't accept data? Would this work? Using an enable/set line
-

 

[michaelst@gmail.com]

You can use FFs with enable.