$setuphold and SDF file

Hi,

In my verilog file I have the following lines:
$setuphold ( posedge CP, posedge E, 0, 0, notify_reg, ,
shcheckCPElh, CPD, ED );
$setuphold ( posedge CP, negedge E, 0, 0, notify_reg, ,
shcheckCPElh, CPD, ED );
$setuphold ( posedge CP, posedge TE, 0, 0, notify_reg, ,
shcheckCPTElh, CPD, TED );
$setuphold ( posedge CP, negedge TE, 0, 0, notify_reg, ,
shcheckCPTElh, CPD, TED );

In my SDF file:
(TIMINGCHECK
(SETUPHOLD (posedge E) (posedge CP) (41.90000::42.00000)
(35.20000::38.00000))
(SETUPHOLD (negedge E) (posedge CP) (28.60000::29.40000)
(15.20000::18.90000))
(SETUPHOLD (posedge TE) (posedge CP) (39.70000::40.50000)
(31.70000::35.40000))
(SETUPHOLD (negedge TE) (posedge CP) (34.40000::32.40000)
(16.10000::19.30000))
)


What is going to happen?
will the numbers at SETUPHOLD replace the numbers at $setuphold?
will the notify reg be changed when the setuphold fail?
what about the other parameters in $setuphold (negative check)?
what is the meaning of having delayed reference signal without delayed
data signal?


Thanks
Pazia