setup and hold violations

[coolblue]

Hi all,
why do we go for worst case PVT conditions for setup violations and
best case PVT conditions for hold violations?
and why not the other way?

Thank you,
Kaushik

 

[Jonathan Bromley]

On 13 Mar 2007 05:31:01 -0700, "coolblue"
<sameerkumarkaushik@gmail.com> wrote:

why do we go for worst case PVT conditions for setup violations and
best case PVT conditions for hold violations?
and why not the other way?

Setup violations are caused because data propagation delay
is too long - for example, if your flipflops' setup time is
10% of a clock cycle then the largest acceptable propagation
delay is 90% of a clock cycle, and 91% is too much.
Clearly this sort of problem will get worse if gate and net
propagation delays become larger. So it's obviously right
to use worst-case (slowest) process/voltage/temperature
(PVT) for setup analysis.

For hold time, things are a little trickier. Hold time violations
are caused because data propagation is *faster* than
clock propagation, and are completely independent of
the clock period. If you assume that clock distribution
delays are fixed, whereas data delays are affected by
PVT, then clearly the best-case (fastest) PVT will
be more likely to evince hold violations. The truth
is more complicated; hold time violations occur when
clock delays and data delays are approximately the
same, and so it is not at all clear to me whether
best or worst PVT is more likely to find a problem.

Others with deeper knowledge of static timing
analysis (STA) may be able to answer in more detail,
but I would want a lot of persuading that best-case
PVT alone is sufficient to smoke-out all hold violations.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Alex]

The truth
is more complicated; hold time violations occur when
clock delays and data delays are approximately the
same, and so it is not at all clear to me whether
best or worst PVT is more likely to find a problem.

Others with deeper knowledge of static timing
analysis (STA) may be able to answer in more detail,
but I would want a lot of persuading that best-case
PVT alone is sufficient to smoke-out all hold violations.

Few more details about hold violations.
In order to lock "next" data in register, the following equation must
hold:

Tco + Tprop > Thold + Tskew

Where
Tco - Clock-to-output delay in register
Tprop - propagation delay from source register to the destination one
Thold - hold time of register
Tskew - clock tree skew.

In order to get to the limits of equation, we have to take best-case
for Tco and Tprop while the worst case for Tskew (assuming Thold is
constant).

So, as Jonatan mentioned, best-case PVT alone is not sufficient,
unless you use in it clock skew calculated with the worst-case PVT.

-Alex

 

[Alex]

For hold time, things are a little trickier. Hold time violations
are caused because data propagation is *faster* than
clock propagation, and are completely independent of
the clock period. If you assume that clock distribution
delays are fixed, whereas data delays are affected by
PVT, then clearly the best-case (fastest) PVT will
be more likely to evince hold violations. The truth
is more complicated; hold time violations occur when
clock delays and data delays are approximately the
same, and so it is not at all clear to me whether
best or worst PVT is more likely to find a problem.

Others with deeper knowledge of static timing
analysis (STA) may be able to answer in more detail,
but I would want a lot of persuading that best-case
PVT alone is sufficient to smoke-out all hold violations.
--

Few more details about hold violations.
In order to lock "next" data in register, the following equation must
hold:

Tco + Tprop > Thold + Tskew

Where
Tco - Clock-to-output delay in register
Tprop - propagation delay from source register to the destination one
Thold - hold time of register
Tskew - clock tree skew.

In order to get to the limits of equation, we have to take best-case
for Tco and Tprop and the maximum value of Tskew (assuming Thold is
constant).

Best-case PVT will provide us with the minimum value for Tco + Tprop.
Maximum Tskew value, however, cannot be derived neither from best not
from worst case PVT. It depends on the quality of clock insertion and
balancing as well on the given technology.


-Alex


-Alex

 

[Alex]

For hold time, things are a little trickier. Hold time violations
are caused because data propagation is *faster* than
clock propagation, and are completely independent of
the clock period. If you assume that clock distribution
delays are fixed, whereas data delays are affected by
PVT, then clearly the best-case (fastest) PVT will
be more likely to evince hold violations. The truth
is more complicated; hold time violations occur when
clock delays and data delays are approximately the
same, and so it is not at all clear to me whether
best or worst PVT is more likely to find a problem.

Others with deeper knowledge of static timing
analysis (STA) may be able to answer in more detail,
but I would want a lot of persuading that best-case
PVT alone is sufficient to smoke-out all hold violations.

Few more details about hold violations.
In order to lock "next" data in register, the following equation must
hold:

Tco + Tprop > Thold + Tskew

Where
Tco - Clock-to-output delay in register
Tprop - propagation delay from source register to the destination one
Thold - hold time of register
Tskew - clock tree skew.

In order to get to the limits of equation, we have to take best-case
for Tco and Tprop and the maximum value of Tskew (assuming Thold is
constant).

Best-case PVT will provide us minimum for Tco + Tprop.
Maximum Tskew value, however, cannot be derived neither from best not
from worst case PVT. It depends on the quality of clock insertion and
balancing as well on the given technology.


-Alex

 

[coolblue]

Thanks to all. i now understand the concept more clearly.

On Mar 13, 11:41 pm, "Alex" <agnu...@gmail.com> wrote:

For hold time, things are a little trickier. Hold time violations
are caused because data propagation is *faster* than
clock propagation, and are completely independent of
the clock period. If you assume that clock distribution
delays are fixed, whereas data delays are affected by
PVT, then clearly the best-case (fastest) PVT will
be more likely to evince hold violations. The truth
is more complicated; hold time violations occur when
clock delays and data delays are approximately the
same, and so it is not at all clear to me whether
best or worst PVT is more likely to find a problem.

Others with deeper knowledge of static timing
analysis (STA) may be able to answer in more detail,
but I would want a lot of persuading that best-case
PVT alone is sufficient to smoke-out all hold violations.

Few more details about hold violations.
In order to lock "next" data in register, the following equation must
hold:

Tco + Tprop > Thold + Tskew

Where
Tco - Clock-to-output delay in register
Tprop - propagation delay from source register to the destination one
Thold - hold time of register
Tskew - clock tree skew.

In order to get to the limits of equation, we have to take best-case
for Tco and Tprop and the maximum value of Tskew (assuming Thold is
constant).

Best-case PVT will provide us minimum for Tco + Tprop.
Maximum Tskew value, however, cannot be derived neither from best not
from worst case PVT. It depends on the quality of clock insertion and
balancing as well on the given technology.

-Alex- Hide quoted text -

- Show quoted text -