setup and hold time violations

[rsk]

Dear Friends,

How to eliminate these violations while doing Static Timing
analysis?What exactly the tool will do for eliminating this.


Thankyou,
krs...

 

[Neo]

The tool wont do anything other than analyze. Its your synthesis tool
which should work on that.

 

[Vinilkant Tejaswi]

I think there are number of techniques that can be employed to remove
the setup and hold violations.

1. Use your synthesis tool to do an optimization on your resulting
netlist. That should help a little.

2. If you are not required to have a fixed clock period, you can
increase the clock period. Essentially you are looking for a positive
slack time.

3. otherwise you can determine the worst case path delay and try to
shorten it by employing ffs, registers. you can also check your RTL
code for this.

I hope this helps
vinil

 

[Vinilkant Tejaswi]

I think there are number of techniques that can be employed to remove
the setup and hold violations.

1. Use your synthesis tool to do an optimization on your resulting
netlist. That should help a little.

2. If you are not required to have a fixed clock period, you can
increase the clock period. Essentially you are looking for a positive
slack time.

3. otherwise you can determine the worst case path delay and try to
shorten it by employing ffs, registers. you can also check your RTL
code for this.

I hope this helps
vinil