setting intital values for synthesis

[Paul Solomon]

Hi Guys/Gals,

Is there an eaisy way to force the initial value of registers for synthesis?
I know you can do it for simulation using an initial clause but I believe
that this wont work for synthesis.

At the moment all the regesters in my design are wired to an async reset, so
when I start my design I have to hit the reset to ensure all the regs are
set to their starting value. However, I assume that there must be a way to
do this automatically, otherwise things like the Nios processor wouldn't
"just work" after programming the image.

I am using Quartus II 4.2 as the synthesis tool at the moment if this is
relevant.

Regards,

Paul Solomon

 

[Chris Briggs]

Actually, normal system design includes having an automatic power-on
reset on the board so your reset logic takes care of initialzing your
registers. If you're using an FPGA eval board that doesn't provide
this, then hitting reset is probably something you're stuck with until
you get to your real board design.

-cb

 

[Ron]

Paul Solomon wrote:

Hi Guys/Gals,

Is there an eaisy way to force the initial value of registers for synthesis?
I know you can do it for simulation using an initial clause but I believe
that this wont work for synthesis.

There are special discrete devices that I think can probably be wired up
externally to do what you want. See for example:
http://xrl.us/gyqf

-- Ron

 

[John_H]

"Chris Briggs" <chris@engim.com> wrote in message
news:1122910019.058544.246630@g49g2000cwa.googlegroups.com...

Actually, normal system design includes having an automatic power-on
reset on the board so your reset logic takes care of initialzing your
registers. If you're using an FPGA eval board that doesn't provide
this, then hitting reset is probably something you're stuck with until
you get to your real board design.

-cb

The "normal system design" you refer to comes from ASICs or from FPGA
designs derived from ASICs.

In the FPGA world, the power-on state of the registers is predefined.

The ability to set the initial state is limited by 1) the synthesis and 2)
the back end FPGA tools.

My design flow includes Synplify_Pro for synthesis and Xilinx back-end
tools. I've been pleading for initial value support from the synthesis
vendor for years. The Xilinx XST synthesizer has support for initial values
(such as "reg MyReg = 1'b1;") but doesn't always produce the same results as
without the initial value. The Xilinx back end tools can force register and
memory initial values with post-synthesis constraints.

I know the default register power-up values for both Altera nad Xilinx FPGAs
is dependent on the kind of set/reset functionality that's "native" to the
primitive instantiated. I don't know if the Altera tools allow that default
value to be changed without an async set/reset applied to force the init
value. ASICs typically rely on the async set/reset for initial states hence
the comment about "normal" design.

I'd like to see power-up initial values become the normal design flow
allowing simulation and synthesis to match without forcing an async
initialization in an architecture that doesn't need it. For now I stick
with the post-synthesis directives for registers where I need defined
power-up states.