Setting a Verilog reg to a character string from ModelSim

[Charles Bailey]

I have a testbench written in Verilog that opens a file and reads source
data from it. I want to pass the name of the file to open from a TCL
command file. According to the Verilog book I have, character strings
can be stored in a reg variable by declaring a reg vector that is n*8
bits long. I am using ModelSim to do the simulation. According to the
ModelSim command reference, the "change" command can be used to set a
Verilog reg. But, it seems that the "change" command wants a bit-string
as the value. Is there any way to set a reg vector to a character
string using the ModelSim "change" command?

Thanks,
Charles Bailey