set_false_path

[fpgaasicdesigner]

Hi,

I have a module generating an internal reset and I would like Design
Compiler to not analyze the timing for this reset path.

I did:
set_false_path -from [get_ports dsp/reset_module/reset_clock_in]

reset_clock_in being the output signal or reset_module block.

But I can see in the timing report this path is analyzed.

Do you know how to tell design compiler to not analyze and internal
signal acting as a reset ?

Thanks

 

[Muzaffer Kal]

On Tue, 27 Apr 2010 10:18:22 -0700 (PDT), fpgaasicdesigner
<fpgaasicdesigner@gmail.com> wrote:

Hi,

I have a module generating an internal reset and I would like Design
Compiler to not analyze the timing for this reset path.

I may have a solution for you but before I tell you what it is, let me

ask you not to use it. You should check timing of your reset signals,
specifically the deactivation of reset signals and if necessary build
a physical tree for your reset.

I did:
set_false_path -from [get_ports dsp/reset_module/reset_clock_in]

You may need to add -hier and/or -net to this command but it's been a
while since I used SDC so this may not apply anymore.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[fpgaasicdesigner]

Hi,

I was thinking the same. As my reset are synchronous, it can generates
bad values at startup if there is a timing violation.
But do I really care, the reset is almost a fixed value, so if it
doesn't reset the registers at time t, it will at time t+T (T:sampling
period) ?

Thanks.

On Apr 28, 12:10 am, Muzaffer Kal <k...@dspia.com> wrote:

On Tue, 27 Apr 2010 10:18:22 -0700 (PDT), fpgaasicdesigner

fpgaasicdesig...@gmail.com> wrote:
Hi,

I have a module generating an internal reset and I would like Design
Compiler to not analyze the timing for this reset path.

I may have a solution for you but before I tell you what it is, let me
ask you not to use it. You should check timing of your reset signals,
specifically the deactivation of reset signals and if necessary build
a physical tree for your reset.

I did:
set_false_path -from [get_ports dsp/reset_module/reset_clock_in]

You may need to add -hier and/or -net to this command but it's been a
while since I used SDC so this may not apply anymore.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

 

[d_s_klein]

On Apr 28, 5:18 am, fpgaasicdesigner <fpgaasicdesig...@gmail.com>
wrote:

Hi,

I was thinking the same. As my reset are synchronous, it can generates
bad values at startup if there is a timing violation.
But do I really care, the reset is almost a fixed value, so if it
doesn't reset the registers at time t, it will at time t+T (T:sampling
period) ?

Thanks.

On Apr 28, 12:10 am, Muzaffer Kal <k...@dspia.com> wrote:

On Tue, 27 Apr 2010 10:18:22 -0700 (PDT), fpgaasicdesigner

fpgaasicdesig...@gmail.com> wrote:
Hi,

I have a module generating an internal reset and I would like Design
Compiler to not analyze the timing for this reset path.

I may have a solution for you but before I tell you what it is, let me
ask you not to use it. You should check timing of your reset signals,
specifically the deactivation of reset signals and if necessary build
a physical tree for your reset.

I did:
set_false_path -from [get_ports dsp/reset_module/reset_clock_in]

You may need to add -hier and/or -net to this command but it's been a
while since I used SDC so this may not apply anymore.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

It's the DE-activation of reset that is timing critical.

And yes, it will bite you.

RK