Serial - parallel conversion problem

[Daku]

Could some Verilog guru please help ? I have a serial parallel
converter that is works as follows:
1. there is no clock, and the input is a serial stream of 1s and
zeros, at a given rate. A second input indicates if the data is valid
(true) or invalid(false).
2. I divide the serial input into 64 a bit array, using the
concatenation operator, and then use a fork - join block to sub-divide
this into 8 8-bit sub-arrays, in parallel
3. I am using Icarus Verilog 0.9.1

However, the output shows that each of the 8-bit sub-arrays contain
0xFF. My source code is given below :
`timescale 10ns/1ns

module rs(pls_data_req,
pls_data_req_incomplete,
txd0,
txd1,
txd2,
txd3,
txd4,
txd5,
txd6,
txd7, txc);
/* txc, tx_clk); */

parameter MAX = 64;
parameter BYTE_SIZE = 8;
parameter BLANK64 =
64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter BLANK8 = 8'b00000000;

input pls_data_req;
input pls_data_req_incomplete;
output [7:0] txd0;
output [7:0] txd1;
output [7:0] txd2;
output [7:0] txd3;
output [7:0] txd4;
output [7:0] txd5;
output [7:0] txd6;
output [7:0] txd7;
output [7:0] txc;
/*
output tx_clk;
*/

integer count;
integer ochnlnum;
reg [63:0] txd;
reg [7:0] txc;
reg [7:0] txd0;
reg [7:0] txd1;
reg [7:0] txd2;
reg [7:0] txd3;
reg [7:0] txd4;
reg [7:0] txd5;
reg [7:0] txd6;
reg [7:0] txd7;

initial
begin
/*
tx_clk = 1b'1;
*/
txd = BLANK64;
txc = 8'b11111111;
count = 0;
ochnlnum = 0;
end

always
#2
begin
if(pls_data_req_incomplete == 1'b1)
begin
for(count = MAX; count > 0; count = count - 1)
begin
txd = {txd[62:0], pls_data_req};
end
fork
assign txd0 = txd[7:0];
assign txd1 = txd[15:8];
assign txd2 = txd[23:16];
assign txd3 = txd[31:24];
assign txd4 = txd[39:32];
assign txd5 = txd[47:40];
assign txd6 = txd[55:48];
assign txd7 = txd[63:56];
join
txd = BLANK64;
$display("txd0=%g txd1=%g txd2=%g txd3=%g txd4=%g",
txd0, txd1, txd2, txd3, txd4);
txd0 = BLANK8;
txd1 = BLANK8;
txd2 = BLANK8;
txd3 = BLANK8;
txd4 = BLANK8;
txd5 = BLANK8;
txd6 = BLANK8;
txd7 = BLANK8;
end
end

endmodule

Any hints, suggestions about what might be going wrong would be
invaluable - I suspect the concatenation step is not working right.
Thanks in advance.

 

[John_H]

On Jul 17, 1:02 am, Daku <dakup...@gmail.com> wrote:

1. there is no clock, and the input is a serial stream of 1s and
zeros, at a given rate. A second input indicates if the data is valid
(true) or invalid(false).

always
 #2
 begin
  if(pls_data_req_incomplete == 1'b1)
  begin
   for(count = MAX; count > 0; count = count - 1)
    begin
     txd = {txd[62:0], pls_data_req};
    end

Any hints, suggestions about what might be going wrong would be
invaluable - I suspect the concatenation step is not working right.
Thanks in advance.

Verilog simulators work on "time steps" where everything evaluated
during the timestep is updated and available for the next timestep's
execution. Once nothing is scheduled for consecutive timesteps, the
simulator can wait for the next time driven event (such as a clock
edge produced from a delay).

In the code I excerted above, you're reading all your bits in
consecutive timesteps which may default to a picosecond each in your
simulator.

Your input serial stream is probably paced in some way. When the
first bit arrives you can't simply "will" that all the bits show up
consecutively in the timesteps that would be convenient for your
receiver. You need to read the data at the pacing established from
the transmitter.


Your serial stream is either asynchronous at a specified rate such
that a downstream clock keys off the req_incomplete flag or you
actually have a serial clock available that you're not using. You
could even have a variable rate (within a defined range) and have the
code figure out what the speed is once the data has been shifted in
with the req_incomplete finally suggesting what the speed was.

You need to put time into your communication (in the sense of a clock)
not just your development (in the sense of developing your code).

 

[WilliamGibb@gmail.com]

Your serial stream is either asynchronous at a specified rate such
that a downstream clock keys off the req_incomplete flag or you
actually have a serial clock available that you're not using.  You
could even have a variable rate (within a defined range) and have the
code figure out what the speed is once the data has been shifted in
with the req_incomplete finally suggesting what the speed was.

You need to put time into your communication (in the sense of a clock)
not just your development (in the sense of developing your code).

OP, consider looking at the source for a UART RX block which does
automatic baud-detection.

Will