Serial Data Capture

[Weddick]

It's been 20 plus years since I did any real design work. I currently am
starting to learn VHDL in order to create a design that will capture serial
data. The serial interface I need to capture data from consists of a 1 Mhz
Clock, Data (32 bits) and Enable signals.

Any help on where to look for examples or how to get started would be
appreciated. If this is the wrong news group, let me know.

Thanks,
Joel

 

[Marc Randolph]

Weddick wrote:

It's been 20 plus years since I did any real design work. I currently am
starting to learn VHDL in order to create a design that will capture serial
data. The serial interface I need to capture data from consists of a 1 Mhz
Clock, Data (32 bits) and Enable signals.

Any help on where to look for examples or how to get started would be
appreciated. If this is the wrong news group, let me know.

Howdy Joel,

The fpga and VHDL news groups seem to support each other sometimes.
This sounds like a purely VHDL question, unless you're trying to do
something fancy or tricky with the FPGA to solve your problem.

You'll probably need to provide a better description of your data stream
to get a good answer on what you need. For example, is the enable like
a sync pulse, where it occurs once per 32 bits, or is it active for each
bit that is valid? If it happens on every bit, how is your circuit
supposed to know which bit on the serial line is to be the MSB of the 32
bit word? Is there a framing sequence in the data?

The fact that the clock is sent along with the data makes this a
relatively straight forward problem. If the enable bit is sent once per
32 bits, it could pre-set a synchronous counter which counts down to 0.
The counter could be used to index into a std_logic_vector(31 downto
0), and when it hit zero, you will have a 32 bit word ready to work
with (latch into a second set of flip flops).

Marc

 

[Weddick]

Thanks for the response. Your description on the data is correct. The
enable is active for the whole 32 bits of data, then goes low for one clock
and then starts over again. I'll check out the VHDL group also.

Joel

"Marc Randolph" <mrand@my-deja.com> wrote in message
news:l7adnSaEOovP6gLdRVn-gQ@comcast.com...

Weddick wrote:
It's been 20 plus years since I did any real design work. I currently
am
starting to learn VHDL in order to create a design that will capture
serial
data. The serial interface I need to capture data from consists of a 1
Mhz
Clock, Data (32 bits) and Enable signals.

Any help on where to look for examples or how to get started would be
appreciated. If this is the wrong news group, let me know.

Howdy Joel,

The fpga and VHDL news groups seem to support each other sometimes.
This sounds like a purely VHDL question, unless you're trying to do
something fancy or tricky with the FPGA to solve your problem.

You'll probably need to provide a better description of your data stream
to get a good answer on what you need. For example, is the enable like
a sync pulse, where it occurs once per 32 bits, or is it active for each
bit that is valid? If it happens on every bit, how is your circuit
supposed to know which bit on the serial line is to be the MSB of the 32
bit word? Is there a framing sequence in the data?

The fact that the clock is sent along with the data makes this a
relatively straight forward problem. If the enable bit is sent once per
32 bits, it could pre-set a synchronous counter which counts down to 0.
The counter could be used to index into a std_logic_vector(31 downto
0), and when it hit zero, you will have a 32 bit word ready to work
with (latch into a second set of flip flops).

Marc