sequential logic issue

[rik]

Hi guys

In the verilog sequential clocked always block what is meant by "clock
used as data"?

Thanks

 

[Enchanter]

I think it should be the clock signal is used as data signal

such as :

always ..
c <= clk
...




rik 写道：

Hi guys

In the verilog sequential clocked always block what is meant by "clock
used as data"?

Thanks