sequential circuits(T-flipflop) in modelsim

[G.K. RAMAM]

i have written the code for T-flipflop at gatelevel using a d-flipflop
and some extra gates.D-flipflop is working fine.The problem is when
the T-flipflop is simulated and the waveforms are observed, the
outputs remain at high impedance state and donot show any change. The
same is the case with jk flipflop implemented at gate level. Now one
can go for behavioral level or higher and can have a working
circuit.But I am trying to do it at gate level.

the code is below
*******************************************************************************
module SR(Q,Qbar,s,r);

output Q,Qbar;
input s,r;

nand(Q,r,Qbar);
nand(Qbar,s,Q);

endmodule

module Dff(Q,Qbar,d,clk);

output Q,Qbar;
input d,clk;

wire w1,w2;

nand(w1,d,clk);
nand(w2,clk,~d);

nand(Q,w1,Qbar);
nand(Qbar,w2,Q);

endmodule

module Tff(Q,Qbar,t,clk);

output Q,Qbar;
input clk,t;

wire w3,w4,w5;

and(w3,Q,~t);
and(w4,Qbar,t);

or(w5,w3,w4);

Dff d1(Q,Qbar,w5,clk);
endmodule
*******************************************************************************

can any body suggest a way around for this problem at gatelevel only.

 

[Swapnajit Mittra]

gkr_ramum@yahoo.com (G.K. RAMAM) wrote in message news:<5d919018.0409111107.7a353b91@posting.google.com>...

i have written the code for T-flipflop at gatelevel using a d-flipflop
and some extra gates.D-flipflop is working fine.The problem is when
the T-flipflop is simulated and the waveforms are observed, the
outputs remain at high impedance state and donot show any change. The
same is the case with jk flipflop implemented at gate level. Now one
can go for behavioral level or higher and can have a working
circuit.But I am trying to do it at gate level.

the code is below
*******************************************************************************
module SR(Q,Qbar,s,r);

output Q,Qbar;
input s,r;

nand(Q,r,Qbar);
nand(Qbar,s,Q);

endmodule

module Dff(Q,Qbar,d,clk);

output Q,Qbar;
input d,clk;

wire w1,w2;

nand(w1,d,clk);
nand(w2,clk,~d);

nand(Q,w1,Qbar);
nand(Qbar,w2,Q);

endmodule

module Tff(Q,Qbar,t,clk);

output Q,Qbar;
input clk,t;

wire w3,w4,w5;

and(w3,Q,~t);
and(w4,Qbar,t);

or(w5,w3,w4);

Dff d1(Q,Qbar,w5,clk);
endmodule
*******************************************************************************

can any body suggest a way around for this problem at gatelevel only.

Can reset play any role here, one wonders.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
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[Swapnajit Mittra]

gkr_ramum@yahoo.com (G.K. RAMAM) wrote in message news:<5d919018.0409111107.7a353b91@posting.google.com>...

i have written the code for T-flipflop at gatelevel using a d-flipflop
and some extra gates.D-flipflop is working fine.The problem is when
the T-flipflop is simulated and the waveforms are observed, the
outputs remain at high impedance state and donot show any change. The
same is the case with jk flipflop implemented at gate level. Now one
can go for behavioral level or higher and can have a working
circuit.But I am trying to do it at gate level.

the code is below
*******************************************************************************
module SR(Q,Qbar,s,r);

output Q,Qbar;
input s,r;

nand(Q,r,Qbar);
nand(Qbar,s,Q);

endmodule

module Dff(Q,Qbar,d,clk);

output Q,Qbar;
input d,clk;

wire w1,w2;

nand(w1,d,clk);
nand(w2,clk,~d);

nand(Q,w1,Qbar);
nand(Qbar,w2,Q);

endmodule

module Tff(Q,Qbar,t,clk);

output Q,Qbar;
input clk,t;

wire w3,w4,w5;

and(w3,Q,~t);
and(w4,Qbar,t);

or(w5,w3,w4);

Dff d1(Q,Qbar,w5,clk);
endmodule
*******************************************************************************

can any body suggest a way around for this problem at gatelevel only.

Can reset play any role here, one wonders.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
For subscribing to the mailing list:
<URL: http://www.project-veripage.com/list/?p=subscribe&id=1>