V
Vivek Menon
Guest
Hi,
I need to generate a sequence "0110". any ideas.
VV
I need to generate a sequence "0110". any ideas.
VV
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Z
Zara
Guest
On 15 Jun 2006 12:23:20 -0700, "Vivek Menon" <vivek.menon79@gmail.com>
wrote:
signal sequence:std_logic_vector(1024 to 1027):="0110";
There you are!
wrote:
Hi,
I need to generate a sequence "0110". any ideas.
signal sequence:std_logic_vector(1024 to 1027):="0110";
There you are!
J
Jonathan Bromley
Guest
On 15 Jun 2006 12:23:20 -0700, "Vivek Menon"
<vivek.menon79@gmail.com> wrote:
problem that's idiotic; no idea about the student).
Hardware has a distressing habit of continuing
to function after you've stopped looking at it.
What, pray, is your sequence generator supposed
to do before, and after, the sequence is generated?
What is the user supposed to do in order to get
the sequence generator to start? And, come to
that, what the hell use is there for a sequence
"0110"?
If academics took a bit more trouble to couch
their problems in a realistic form rather than
providing trivial exercises that match their
favourite page in the textbook, then the
engineering profession as a whole would
be in much better shape, and their students
would be more likely to want to solve the
problems for themselves and less likely
to come whingeing to the newsgroups.
Speaking, through gritted teeth, as one who
spent a fair few years dreaming-up student
homework assignments...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
<vivek.menon79@gmail.com> wrote:
Typical idiotic student homework problem (it's theI need to generate a sequence "0110". any ideas.
problem that's idiotic; no idea about the student).
Hardware has a distressing habit of continuing
to function after you've stopped looking at it.
What, pray, is your sequence generator supposed
to do before, and after, the sequence is generated?
What is the user supposed to do in order to get
the sequence generator to start? And, come to
that, what the hell use is there for a sequence
"0110"?
If academics took a bit more trouble to couch
their problems in a realistic form rather than
providing trivial exercises that match their
favourite page in the textbook, then the
engineering profession as a whole would
be in much better shape, and their students
would be more likely to want to solve the
problems for themselves and less likely
to come whingeing to the newsgroups.
Speaking, through gritted teeth, as one who
spent a fair few years dreaming-up student
homework assignments...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
D
dipesh.trivedi
Guest
hey buddy,
u just have to do is. reset the counter with the required sequence. n
then
assign it within the clock. i mean to say u can make the ring counter
which will provide u with the sequence generator.
signal seq: std_logic_vector (3 downto 0);
process( clk)
begin
if ( reset = '1')
seq <= "0110";
elsif (clk'event and clk = '1') then
seq <= seq (0) & seq( 3 downto 1);
end if ;
end process;
i hope its write. neways am writting code in VHDL aftr 2 years.
if am wrong pls correct me.
Jonathan Bromley wrote:
u just have to do is. reset the counter with the required sequence. n
then
assign it within the clock. i mean to say u can make the ring counter
which will provide u with the sequence generator.
signal seq: std_logic_vector (3 downto 0);
process( clk)
begin
if ( reset = '1')
seq <= "0110";
elsif (clk'event and clk = '1') then
seq <= seq (0) & seq( 3 downto 1);
end if ;
end process;
i hope its write. neways am writting code in VHDL aftr 2 years.
if am wrong pls correct me.
Jonathan Bromley wrote:
On 15 Jun 2006 12:23:20 -0700, "Vivek Menon"
vivek.menon79@gmail.com> wrote:
I need to generate a sequence "0110". any ideas.
Typical idiotic student homework problem (it's the
problem that's idiotic; no idea about the student).
Hardware has a distressing habit of continuing
to function after you've stopped looking at it.
What, pray, is your sequence generator supposed
to do before, and after, the sequence is generated?
What is the user supposed to do in order to get
the sequence generator to start? And, come to
that, what the hell use is there for a sequence
"0110"?
If academics took a bit more trouble to couch
their problems in a realistic form rather than
providing trivial exercises that match their
favourite page in the textbook, then the
engineering profession as a whole would
be in much better shape, and their students
would be more likely to want to solve the
problems for themselves and less likely
to come whingeing to the newsgroups.
Speaking, through gritted teeth, as one who
spent a fair few years dreaming-up student
homework assignments...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.