sequence detector problem

I am working on this code and would like to know why isn't my
waveforms coming out correctly in my testbench.
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//Sequence Detector
//April 15, 2007

module SequenceDetect(INPUT_S, CLK, START, F, A, D, RST);
//input and output of the state machine(controller)
input INPUT_S, CLK, START;
input RST;
output reg A, D, F;

//"binary encoding"
parameter st0 = 0000;
parameter st1 = 0001;
parameter st2 = 0010;
parameter st3 = 0011;
parameter st4 = 0100;
parameter st5 = 0101;
parameter st6 = 0110;
parameter st7 = 0111;
parameter ABORT = 1000;
parameter DESTUFF = 1001;
parameter FLAG = 1010;

//next state(D) and current state(state register/Q)
reg [3:0] NS, CS;

//code the state register
always @ (posedge CLK or posedge RST)
begin
if(RST)
begin
CS = st0;
end
else
begin
CS = NS;
end
end

//code the next state combinational logic
always @ (INPUT_S or CS or START)

begin
case(CS)

st0: begin if(~INPUT_S) NS <= st1;
else NS <= st0; end

st1: begin if(INPUT_S) NS <= st2;
else NS <= st1; end

st2: begin if(INPUT_S) NS <= st3;
else NS <= st1; end

st3: begin if(INPUT_S) NS <= st4;
else NS <= st1; end

st4: begin if(INPUT_S) NS <= st5;
else NS <=st1; end

st5: begin if(INPUT_S) NS <= st6;
else NS <= st1; end

st6: begin if(INPUT_S) NS <= st7;
else NS <= DESTUFF; end

st7: begin if(INPUT_S) NS <= ABORT;
else NS <= FLAG; end
DESTUFF: begin if(INPUT_S) NS<= st0;
else NS <= st1; end

FLAG: begin if(INPUT_S) NS<= st0;
else NS <= st1; end

ABORT: begin if(INPUT_S) NS<=st0;
else NS <= st1; end
default:
NS <= st0;
endcase
end

//output combination logic
always @ (CS)
begin
case (CS)
DESTUFF:begin
A=0; D=1; F=0 ;
end
FLAG:begin
A=0; D=0; F=1 ;
end
ABORT:begin
A=1; D=0; F=0 ;
end
default:begin
A=0; D=0; F=0 ;
end
endcase

end

endmodule
=====================
//Verilog Code: LAB 7
//Sequence Detector
//April 15, 2007

module SequenceDetect_TB();
reg INPUT_S_TB, RST_TB,START_TB, CLK_TB;
wire FLAG_TB, ABORT_TB, DESTUFF_TB;

SequenceDetect U0
(.INPUT_S(INPUT_S_TB), .RST(RST_TB), .START(START_TB), .CLK(CLK_TB), .F(FLAG_TB), .A(ABORT_TB), .D(DESTUFF_TB));

initial
begin

RST_TB <= 1;
CLK_TB <= 0;
START_TB <= 0;
INPUT_S_TB <=0;

#30 START_TB <= 1;
RST_TB <= 0;

#100 INPUT_S_TB=0;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;
#100 INPUT_S_TB=1;//a
#30 $stop;
#20 $finish;
end

always #50 CLK_TB <= ~CLK_TB;
endmodule
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