Separating control and data paths

[crazyrdx]

I have read that simulation is much better if there is a clear
separation of control and data paths in VHDL. Can someone give me an
example code of this?

thanks
RP

 

[Marcus Harnisch]

Hi RP,

"crazyrdx" <RishiRP@gmail.com> writes:

I have read that simulation is much better if there is a clear
separation of control and data paths in VHDL. Can someone give me an
example code of this?

I am not sure about getting "better" simulation results, whatever that
means. To me it's more a matter of coding style (which in turn is
often a matter of the targeted application), similar to the never
ending discussions about the benefits of 1/2/3-process FSMs. Actually,
a 2+-process FSM separates control and data paths as well.

OK, here's my example. Think of a register file with N registers. You
could separate the address decoding logic (control path) from register
assignment (data path). Your address decoder would translate the
address to a more abstract representation.

case addr
[...]
when "0101010" => enable_reg <= 99; -- the binary address doesn't have to
-- correspond with the actual index

[...]

end case;

-- this goes into a clocked process
reg[enable_reg] <= data;



Regards,
Marcus

 

[Mike Treseler]

crazyrdx wrote:

I have read that simulation is much better if there is a clear
separation of control and data paths in VHDL. Can someone give me an
example code of this?

I agree with Marcus.
This is a style issue with little
or no effect on sim time or synthesis utilization.
If you feel the need to draw a schematic
and follow the data through it as an
ad hoc simulation of the design you might
prefer multiple processes for data and
control.

Example:
trace the data flow from Tx_v in this schematic:
http://home.comcast.net/~mike_treseler/uart.pdf

If you feel comfortable following data
identifiers through a text logic description
and checking operation from simulation
waveforms, then synthesis will draw
the schematic for you, no matter how
complicated the design is. In this
case, I find a single process design
easier to follow.

Example:
Find all occurrences of the identifier
Tx_v in this logic description:
http://home.comcast.net/~mike_treseler/uart.vhd
Check the Tx_v waveform here:
http://home.comcast.net/~mike_treseler/uart_sim.pdf
and find all occurrences of the value 0C in
all waveforms.


-- Mike Treseler

 

[crazyrdx]

thanks for your replies.

So as I understand it, this is just about coding style. Wouldnt it mean
that the hardware result is much closer to what we expect if we did it
manually?(thats what i meant by better)?

RP

 

[Mike Treseler]

crazyrdx wrote:

thanks for your replies.

So as I understand it, this is just about coding style. Wouldnt it mean
that the hardware result is much closer to what we expect if we did it
manually?(thats what i meant by better)?

No, the synthesis result would be the same for equivalent
descriptions with different styles.

_Better_ means whatever is easier
for you to understand and simulate.

-- Mike Treseler