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It's legal Verilog syntax, but is almost certainlyHi,
Can I use any other variables in the sensitivity list
along with the clock?
For eg : always @ (posedge clock, a, var)
Is the example above a legal syntax?
On Thu, 24 Jan 2008 00:05:50 -0800 (PST),
avisheksah...@gmail.com wrote:
Hi,
Can I use any other variables in the sensitivity list
along with the clock?
For eg : always @ (posedge clock, a, var)
Is the example above a legal syntax?
It's legal Verilog syntax, but is almost certainly
broken for synthesis.
Why do you wish to do this? It may be that there's
a more reliable way...
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
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