Sending and receiving Ethernet traffic

J

Jean Nicolle

Guest
I managed to transmit and receive traffic on a 10BASE-T network using some
simple Verilog code and 4 pins of an FPGA connected almost directly to the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems that we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean
 
BTW, the statement about 4 pins is not correct.
I use 2 pins for transmission, but only 1 pin for reception (I have 2
transistors to create a differential input from the 10BASE-T RD+/RD- wires
to the FPGA).

"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message
news:XuX5b.5$Y15.5657658@newssvr13.news.prodigy.com...
I managed to transmit and receive traffic on a 10BASE-T network using some
simple Verilog code and 4 pins of an FPGA connected almost directly to the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems that
we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean
Click to expand...
 
I managed to transmit and receive traffic on a 10BASE-T network using some
simple Verilog code and 4 pins of an FPGA connected almost directly to the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems that
we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean
Click to expand...
Cool project. Have you coded the ethernet stuff by yourself or used an ip
block? You have one small misstake: The splitting in RX and TX lines on RJ45
does not prevent contention! It is still possible. Some time ago I was also
thinking about an ethernet inteface in an FPGA. I thought, like you, now
with RJ45 it's easier since contention detection is one of the hard parts.
However, if you read carefully the doc's it's still there ;-(

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
 
Martin,

about the contention, in the current IEEE spec (IEEE 802.3-2002), section
"4.2.3.2.6 Full duplex transmission" states:
"In full duplex mode, there is never contention for a shared physical
medium."

That's the beauty of it. Twice the bandwidth, and much easier to implement.
So my code is only intended to be connected to a full-duplex capable device
only (i.e. a switch or directly to another computer).

Your remark is true for half-duplex (which is much harder to implement!).
Hope that convinces you.
Jean

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:AJ47b.216558$2k4.2477739@news.chello.at...
I managed to transmit and receive traffic on a 10BASE-T network using
some
simple Verilog code and 4 pins of an FPGA connected almost directly to
the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems
that
we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean


Cool project. Have you coded the ethernet stuff by yourself or used an ip
block? You have one small misstake: The splitting in RX and TX lines on
RJ45
does not prevent contention! It is still possible. Some time ago I was
also
thinking about an ethernet inteface in an FPGA. I thought, like you, now
with RJ45 it's easier since contention detection is one of the hard parts.
However, if you read carefully the doc's it's still there ;-(

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Click to expand...
 
Jean,

there is still a problem. If you use a point to point connection (with a
cross over cabel) it can be possible that both stations transmit without a
contention. However, Ethernet is still a bus. Imagine following situation:
Three stations (A,B,C) connected via a hub. Station A and B are sending at
the same time. Which message will arrive at C? This IS a contention. On A
and B perhaps you will not see a contention on the TX lines, however you
have to listen to the RX line while sending and abort your transmit, enter
the random timeout and retransmit.
And I'm not shure if a simple hub will support full duplex mode.

Sorry, I'm not convinced

Martin

Martin,

about the contention, in the current IEEE spec (IEEE 802.3-2002), section
"4.2.3.2.6 Full duplex transmission" states:
"In full duplex mode, there is never contention for a shared physical
medium."

That's the beauty of it. Twice the bandwidth, and much easier to
implement.
So my code is only intended to be connected to a full-duplex capable
device
only (i.e. a switch or directly to another computer).

Your remark is true for half-duplex (which is much harder to implement!).
Hope that convinces you.
Jean

"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:AJ47b.216558$2k4.2477739@news.chello.at...
I managed to transmit and receive traffic on a 10BASE-T network using
some
simple Verilog code and 4 pins of an FPGA connected almost directly to
the
wires.

Most microcontrollers require an external Ethernet MAC, but it seems
that
we
can do without if we limit ourselves to IP/UDP.
I think that there are potentially plenty of interesting applications.

The project is working well already, so I documented a good chunk of
it.
http://www.fpga4fun.com/10BASE-T.html

Comments are welcome!
Jean


Cool project. Have you coded the ethernet stuff by yourself or used an
ip
block? You have one small misstake: The splitting in RX and TX lines on
RJ45
does not prevent contention! It is still possible. Some time ago I was
also
thinking about an ethernet inteface in an FPGA. I thought, like you, now
with RJ45 it's easier since contention detection is one of the hard
parts.
However, if you read carefully the doc's it's still there ;-(

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Click to expand...
 
On Tue, 09 Sep 2003 06:39:16 GMT, "Martin Schoeberl"
<martin.schoeberl@chello.at> wrote:

Jean,

there is still a problem. If you use a point to point connection (with a
cross over cabel) it can be possible that both stations transmit without a
contention. However, Ethernet is still a bus. Imagine following situation:
Three stations (A,B,C) connected via a hub.
Click to expand...
Jean is only supporting full duplex mode on point to point links,
which disallows the use of a hub.

Regards,
Allan.
 
Followup to: <oAe7b.2784$ef4.20589@news.chello.at>
By author: "Martin Schoeberl" <martin.schoeberl@chello.at>
In newsgroup: comp.arch.fpga
Jean,

there is still a problem. If you use a point to point connection (with a
cross over cabel) it can be possible that both stations transmit without a
contention. However, Ethernet is still a bus.
Click to expand...
Full-duplex Ethernet is *not* a bus and does *not* use CSMA/CD. It's
a point-to-point self-clocking serial connection. All
interconnections have to be done at layer 2 (i.e. by bridges/switches)
or higher.

-hpa
--
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64
 
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