Semi Foundry Economics

[Spehro Pefhany]

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Spehro Pefhany]

On Sat, 26 Feb 2011 20:25:58 +0000 (UTC), the renowned Cydrome Leader
<presence@MUNGEpanix.com> wrote:

Spehro Pefhany <speffSNIP@interlogdotyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.


Best regards,
Spehro Pefhany

how much is a mask cost?

Quite variable.. area (and also resolution) make a huge difference. Of
course you need one mask for every layer, so it's * n. Apparently for
state-of-the art resolution and wafer size, it's in the $millions for
a set. My test will not cost nearly that much. NRE for a mask ROM
(single layer customized) used to be in the $1-2K range, IIRC.

I've always wondered what the price is to ramp up to make those custom
epoxy blob ICs on cheap electronics like toys, calculators and watches.

Not sure how 'custom' those really are.



Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[Cydrome Leader]

Spehro Pefhany <speffSNIP@interlogdotyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.


Best regards,
Spehro Pefhany

how much is a mask cost?

I've always wondered what the price is to ramp up to make those custom
epoxy blob ICs on cheap electronics like toys, calculators and watches.

 

[linnix]

On Feb 26, 11:29 am, Spehro Pefhany
<speffS...@interlogDOTyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

It depends on the processes, layers, thickness and geometries.
Without knowing
the exact requirements, it's difficult to estimate fixed cost, let
alone incremental cost.
If you tell me more about your device (perhaps NDA), I can tell you
more about the cost.

 

[Jim Thompson]

On Sat, 26 Feb 2011 14:29:54 -0500, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

"Done" ?? Where? Have you looked into MOSIS? They do MPW's
(multi-project wafers) for almost every foundry in the world. And
they will price out all of your questions.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.


Best regards,
Spehro Pefhany

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

Remember: Once you go over the hill, you pick up speed

 

[miso@sushi.com]

On Feb 26, 11:29 am, Spehro Pefhany
<speffS...@interlogDOTyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Generally the process is set up so that you are not tweaking anything
along the line for a particular product, so there isn't a setup for
each stage other than loading the mask. I believe ion implanters are
the exception here since the implanter can be shared between
processes, or the company uses an outside service for implants. Many
a water run has been screwed up by incorrectly set up implants.

At some point of scale, the process line does get tweaked for the
product, but that would be a case where the process line is dedicated
to one product. And not every manufacturer does this.

I have to wonder about the "maybe silicon" comment. You request is
quite vague. But you would be a fool not to get the production cost
before you even start the development phase, so the whole question is
dubious.

There are other elements in the cost of the final product. Packaging
low volume chips won't be cheap. Is your lead frame a custom? Stamped
or etched? Do you need backlap?

If you really are making a MEMS, does the fab have some sort of item
in the test pattern that will correlate to the viability of your
structure? This probably needs some more explanation. When you process
wafers, there are test patterns on the wafer. The devices on the test
pattern have limits. You get the right to refuse buying the wafer if
the test criteria isn't met. The goal here is to isolate whose fault
is it that the product doesn't yield. Now if there is no MEMS on the
test pattern, then you have less assurance that the wafers will yield,
and you have no recourse in refusing them.

 

[linnix]

On Feb 26, 7:18 pm, "m...@sushi.com" <m...@sushi.com> wrote:

On Feb 26, 11:29 am, Spehro Pefhany



speffS...@interlogDOTyou.knowwhat> wrote:
I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Generally the process is set up so that you are not tweaking anything
along the line for a particular product, so there isn't a setup for
each stage other than loading the mask.

Thinking MEMS. They almost certainly need to tweak the process for
implant/etch/trim.

I believe ion implanters are
the exception here since the implanter can be shared between
processes, or the company uses an outside service for implants.  Many
a water run has been screwed up by incorrectly set up implants.

Most fabs have in-house implanter. If they can afford air filters
(for the clean room), they can afford implanters.

 

[legg]

On Sat, 26 Feb 2011 19:08:17 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sat, 26 Feb 2011 14:29:54 -0500, Spehro Pefhany
speffSNIP@interlogDOTyou.knowwhat> wrote:


I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

"Done" ?? Where? Have you looked into MOSIS? They do MPW's
(multi-project wafers) for almost every foundry in the world. And
they will price out all of your questions.

Not sure that MicroElectroMechanical etching is a run of the mill
process step for standard CMOS.

RL

 

[Spehro Pefhany]

On Sun, 27 Feb 2011 09:03:27 -0500, the renowned legg
<legg@nospam.magma.ca> wrote:

On Sat, 26 Feb 2011 19:08:17 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sat, 26 Feb 2011 14:29:54 -0500, Spehro Pefhany
speffSNIP@interlogDOTyou.knowwhat> wrote:


I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

"Done" ?? Where? Have you looked into MOSIS? They do MPW's
(multi-project wafers) for almost every foundry in the world. And
they will price out all of your questions.

Not sure that MicroElectroMechanical etching is a run of the mill
process step for standard CMOS.

RL

Yup. There's really only one or two foundries in the world wot have a
handle on this stuff, and not only can't I talk about it, but it's so
far off the chart in several ways that it wouldn't help.

But from a process pov it isn't much different from making a 100mm
wafer full of 555s, in a run of 1-5 wafers.

So is making a 'run' of 1 wafer vs. 5 wafers (ignoring substrate cost)
double the work? 25% more?


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com

 

[linnix]

"Done" ??  Where?  Have you looked into MOSIS?  They do MPW's
(multi-project wafers) for almost every foundry in the world.  And
they will price out all of your questions.

Very difficult to merge unrelated MEMS projects.

Not sure that MicroElectroMechanical etching is a run of the mill
process step for standard CMOS.

MEMS growing/etching/trimming is anything but standard, other than the
equipments and clean rooms.

RL

Yup. There's really only one or two foundries in the world wot have a
handle on this stuff, and not only can't I talk about it, but it's so
far off the chart in several ways that it wouldn't help.  

Even with NDA, the fabs won't disclose what they do for other
customers. But for 20K, they will guide us away from mistakes.

But from a process pov it isn't much different from making a 100mm
wafer full of 555s, in a run of 1-5 wafers.

So is making a 'run' of 1 wafer vs. 5 wafers (ignoring substrate cost)
double the work? 25% more?

It depends, growing/etching may be 25% to 50% more. Trimming may be
125% more. The reason MEMS is popular with 100mm is that some of
these order equipments can't handle more than 1 or 2 wafers. So, they
are dirt cheap, relative to the 150mm or 200mm equipments.
 

 

[miso@sushi.com]

On Feb 26, 7:39 pm, linnix <m...@linnix.info-for.us> wrote:

On Feb 26, 7:18 pm, "m...@sushi.com" <m...@sushi.com> wrote:



On Feb 26, 11:29 am, Spehro Pefhany

speffS...@interlogDOTyou.knowwhat> wrote:
I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Generally the process is set up so that you are not tweaking anything
along the line for a particular product, so there isn't a setup for
each stage other than loading the mask.

Thinking MEMS.  They almost certainly need to tweak the process for
implant/etch/trim.

I believe ion implanters are
the exception here since the implanter can be shared between
processes, or the company uses an outside service for implants.  Many
a water run has been screwed up by incorrectly set up implants.

Most fabs have in-house implanter.  If they can afford air filters
(for the clean room), they can afford implanters.

You realize an implanter is about $4 million. I've worked at semis
that used outside implanters.
http://www.innovioncorp.com/
One of a handfull that do implants.

If the original poster is going to a fab, the fab is not going to
tweak the process. With a fab, what you see is what you get. If you
need something custom, that is a big deal. I've worked at fabless
semis where we set up our own tweaks, but we are talking serious
bucks.

 

[miso@sushi.com]

On Feb 27, 7:30 am, Spehro Pefhany <speffS...@interlogDOTyou.knowwhat>
wrote:

On Sun, 27 Feb 2011 09:03:27 -0500, the renowned legg



l...@nospam.magma.ca> wrote:
On Sat, 26 Feb 2011 19:08:17 -0700, Jim Thompson
To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> wrote:

On Sat, 26 Feb 2011 14:29:54 -0500, Spehro Pefhany
speffS...@interlogDOTyou.knowwhat> wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

"Done" ??  Where?  Have you looked into MOSIS?  They do MPW's
(multi-project wafers) for almost every foundry in the world.  And
they will price out all of your questions.

Not sure that MicroElectroMechanical etching is a run of the mill
process step for standard CMOS.

RL

Yup. There's really only one or two foundries in the world wot have a
handle on this stuff, and not only can't I talk about it, but it's so
far off the chart in several ways that it wouldn't help.  

But from a process pov it isn't much different from making a 100mm
wafer full of 555s, in a run of 1-5 wafers.

So is making a 'run' of 1 wafer vs. 5 wafers (ignoring substrate cost)
double the work? 25% more?  

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Trust me, you never make a one wafer run. Shit happens, especially on
prototypes. Assuming you are not doing a multichip, the cost of
tooling will be more significant than the wafer cost.

 

[Jon Elson]

On 02/26/2011 01:29 PM, Spehro Pefhany wrote:

I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).
Well, we get some .5 uM mixed-signal chips made through MOSIS for about

$12,000 for a chip of about 3 x 5 mm. This is on the old AMI CMOS
process, now apparently owned by ON Semi. For that price, we get 40
pieces, and that is a mixed run, combined with other chips from other
groups.
They are U-test-em, just singulated and packaged.

The price goes up almost linearly to about 200 parts, then it starts to
level off dramatically. We've never had more than a few hundred parts
made at a time.

Jon

 

[linnix]

On Feb 27, 10:49 pm, "m...@sushi.com" <m...@sushi.com> wrote:

On Feb 26, 7:39 pm, linnix <m...@linnix.info-for.us> wrote:



On Feb 26, 7:18 pm, "m...@sushi.com" <m...@sushi.com> wrote:

On Feb 26, 11:29 am, Spehro Pefhany

speffS...@interlogDOTyou.knowwhat> wrote:
I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Generally the process is set up so that you are not tweaking anything
along the line for a particular product, so there isn't a setup for
each stage other than loading the mask.

Thinking MEMS.  They almost certainly need to tweak the process for
implant/etch/trim.

I believe ion implanters are
the exception here since the implanter can be shared between
processes, or the company uses an outside service for implants.  Many
a water run has been screwed up by incorrectly set up implants.

Most fabs have in-house implanter.  If they can afford air filters
(for the clean room), they can afford implanters.

You realize an implanter is about $4 million.

Clean room would cost more than that. If they don't do implant, what
else do that do?

I've worked at semis that used outside implanters.

A fabless semi (as you said) which is not a real fab.

http://www.innovioncorp.com/
One of a handfull that do implants.

If the original poster is going to a fab, the fab is not going to
tweak the process. With a fab, what you see is what you get.

Then you won't be able to build MEMS there.

If you
need something custom, that is a big deal. I've worked at fabless
semis where we set up our own tweaks, but we are talking serious
bucks.

True and necessary, unfortunately.

 

[miso@sushi.com]

On Feb 28, 7:11 pm, linnix <m...@linnix.info-for.us> wrote:

On Feb 27, 10:49 pm, "m...@sushi.com" <m...@sushi.com> wrote:



On Feb 26, 7:39 pm, linnix <m...@linnix.info-for.us> wrote:

On Feb 26, 7:18 pm, "m...@sushi.com" <m...@sushi.com> wrote:

On Feb 26, 11:29 am, Spehro Pefhany

speffS...@interlogDOTyou.knowwhat> wrote:
I'm getting a very small (test) specialized wafer run done (think MEMS
or something along those lines). Probably on 100mm wafers, probably
silicon.

Any rough rules of thumb for what the incremental process cost of
running additional wafers will be? There's mask cost, which could be
considered fixed, and presumably some setup for each process stage and
each run, then a variable cost dependent on how many wafers are run in
each batch (substrate cost would figure into the latter).

Thanks for any info.

Best regards,
Spehro Pefhany
--
"it's the network..."                          "The Journey is the reward"
sp...@interlog.com             Info for manufacturers:http://www.trexon.com
Embedded software/hardware/analog  Info for designers:  http://www.speff.com

Generally the process is set up so that you are not tweaking anything
along the line for a particular product, so there isn't a setup for
each stage other than loading the mask.

Thinking MEMS.  They almost certainly need to tweak the process for
implant/etch/trim.

I believe ion implanters are
the exception here since the implanter can be shared between
processes, or the company uses an outside service for implants.  Many
a water run has been screwed up by incorrectly set up implants.

Most fabs have in-house implanter.  If they can afford air filters
(for the clean room), they can afford implanters.

You realize an implanter is about $4 million.

Clean room would cost more than that.  If they don't do implant, what
else do that do?

I've worked at semis that used outside implanters.

A fabless semi (as you said) which is not a real fab.

http://www.innovioncorp.com/
One of a handfull that do implants.

If the original poster is going to a fab, the fab is not going to
tweak the process. With a fab, what you see is what you get.

Then you won't be able to build MEMS there.

If you
need something custom, that is a big deal. I've worked at fabless
semis where we set up our own tweaks, but we are talking serious
bucks.

True and necessary, unfortunately.

I guess English isn't your first language. Let me try this again. When
you work at a fabless semi, you deal with an outside fab. You can, if
you have the personnel in-house, set up a process in that outside fab.
Of course, this takes money and the clout that goes with it. You may
have to buy some gear for that outside fab. A sputterer for thin film
is a prime example since very few fabs can do thin film or even
require it.

The clean room is step number one. You don't have a fab without a
clean room. That is money you are required to spend if you want to be
in the business. However, you can have a fab that does some steps,
such as the ion implantation, out of the fab. The fact these outside
implant services exist is evidence some companies use them.

This is all part of the Silicon Valley culture. Most of these outside
companies doing semi services are start-ups from employees in the
valley. Implanters, fib, backlap, FA, etc. You simply can't thow a
million here and there and control your cash flow, nor can a small
company keep expensive fab items utilized 100%. Bean counters like to
expense. They don't like to buy and then depreciate.

Semis startups are not what the venture market wants these days, or
even for the last decade.. Venture capitalists don't dump piles of
money on what they consider old technology. Cash flow is a big deal,
and the less venture you take, the more the employees (well founders)
make. So you start fabless, then buy an old fab or build one if you
have volume, but even that has to be done on the cheap.