Self-check Testbench Learning

[Davy]

Hi all,

I am a fresh algorithm HDL designer(mainly concern DSP algorithm HDL
realize).
And I am new to self-check testbench. I have get a book named "Writing
Testbench", but it seems mainly about protocal and bus HDL.

Is there any other resource to learn testbench skills?

BTW, I use Verilog.

Any suggestions will be appreciated!
Best regards,
Davy