Selectively disable timing check?

[Kelvin Tsai @ Singapore]

Hi, all:

My design includes a RAM simulation model but now I need to run a zero
delay simulation on the chip(gate level). My library uses 1ns for each
cell, and I used +delay_mode_zero to disable it...however this causes
malfunction in the RAM I guess.

I want to know how to handle this situation?

Best Regards,
Kelvin.

 

[Andy]

Thank you Steven!

I will check out the manuals of NC-Verilog and Verilog-XL. If they support
such system tasks it would be great.

However, could you teach me something about this?
What is the right procedure to synthesize a design with a RAM when I don't
have a .db model for the
RAM? I only have the datasheet and .lib file generated from a RAM-Generator
supplied by the fab.

Best Regards,
Kelvin





"Steven Sharp" <sharp@cadence.com> wrote in message
news:3a8e124e.0309081039.5f859d3f@posting.google.com...

kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) wrote in message
news:<bf7e7c6.0309080101.4ecbc744@posting.google.com>...

There are generally command line options that will disable all
timing checks. If you want to selectively disable timing warnings
for one part of the design, you can check whether your simulator
supports the $disable_warnings system task. If so, then this
can be used to disable timing checks for specific module instances
and the hierarchy under them. The syntax would be

$disable_warnings("timing", module_inst1, module_inst2, ...);

I don't know whether this will disable other effects of timing
checks, such as notifier toggling.