Segmentation fault in Verilog Code.

[priya]

Hi ..

I am using modelsim tool to simulate the verilog code and
also interfacing Verilog with Vpi..

I have written Vhdl and vpi code for decoder .

I got the following error while running the Code.
# Program received signal SIGSEGV, Segmentation fault
# 0x004e33ab in vsimk!vpi_put_value ()


Someone help me on this ....


I ran the same verilog and vpi code using icarus tool.Its is working
fine....

I dont know why its creating problem while using modelsim...



regds,
priya