Seek clarification on unusual Verilog notattion

[Daku]

Could some Verilog guru please clarify the following
notation ?

inv #(1) d0_0 (
..in(din[0:0]),
..out(dout[0:0])
);

In this case, what does the "#(1)" mean ?
Thanks in advance for your help.

 

[Cary R.]

On 8/24/2011 9:33 AM, Daku wrote:

Could some Verilog guru please clarify the following
notation ?

inv #(1) d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);

In this case, what does the "#(1)" mean ?
Thanks in advance for your help.

This is how a parameter is passed to a module during instantiation. You
need to look at the inv module to understand what the parameter is
actually being used for (e.g. the width of the input, etc.).

Cary

 

[Stephen Williams]

On 08/24/2011 11:53 AM, Cary R. wrote:

On 8/24/2011 9:33 AM, Daku wrote:
Could some Verilog guru please clarify the following
notation ?

inv #(1) d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);

In this case, what does the "#(1)" mean ?
Thanks in advance for your help.

This is how a parameter is passed to a module during instantiation. You
need to look at the inv module to understand what the parameter is
actually being used for (e.g. the width of the input, etc.).

.... Except that "inv" is a primitive in this case, and the parameter
is interpreted as a gate delay in the current timescale.

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Mark Curry]

In article <ICd5q.55146$Z71.34324@newsfe21.iad>,
Stephen Williams <spamtrap@icarus.com> wrote:

On 08/24/2011 11:53 AM, Cary R. wrote:
On 8/24/2011 9:33 AM, Daku wrote:
Could some Verilog guru please clarify the following
notation ?

inv #(1) d0_0 (
.in(din[0:0]),
.out(dout[0:0])
);

In this case, what does the "#(1)" mean ?
Thanks in advance for your help.

This is how a parameter is passed to a module during instantiation. You
need to look at the inv module to understand what the parameter is
actually being used for (e.g. the width of the input, etc.).

... Except that "inv" is a primitive in this case, and the parameter
is interpreted as a gate delay in the current timescale.

"inv" isn't a built-in primitive. "not" is.

Very likely that whomever created it may have modeled it as such, and the #1 COULD
mean the same thing... But Cary's response is more accurate. Check the
module for definition.

--Mark