secondary turn-on

[Anthony C Smith]

Hi I am using the HIP4081 driving a H bridge with 4 STP24NF10 fets-
Gate resistors are 10R in high side fets, 33R in low side, all drive R's
have 1n4148 discharge diodes to speed turn off-
circuit functions well -except for a 5n pulse on the low fet coincident with
the turn on of the high fet- PCB is layed out to full guidelines from harris
including laying gate traces with source feed on underside as plane to
reduce the chance of this phenomina-

any usefull ideas on reducing this- unit works well but this is obviously
wasting power and heating the low side fet (although even without sink its
mostly cold)

Regards

Anthony C Smith

 

[Winfield Hill]

Anthony C Smith wrote...

Hi. I am using the HIP4081 driving a H bridge with 4 STP24NF10
fets- Gate resistors are 10R in high side fets, 33R in low side,
all drive R's have 1n4148 discharge diodes to speed turn off ...

Whoa! The HIP4081 can source/sink several amps to the FET gates,
far too much for wimpy '4148 diodes. For fast turnoff you want
to keep the sink-path voltage drops as low as possible; so use
1n5817 Schottky diodes. Also, along the same vein of thought,
never use logic-level FETs in an application like this. I made
that mistake ... once.


--
Thanks,
- Win

 

[Fritz Schlunder]

"Anthony C Smith" <acs@mapsoncurrent-thinking.com> wrote in message
news:cosd5b$khm$1@sparta.btinternet.com...

Hi I am using the HIP4081 driving a H bridge with 4 STP24NF10 fets-
Gate resistors are 10R in high side fets, 33R in low side, all drive R's
have 1n4148 discharge diodes to speed turn off-
circuit functions well -except for a 5n pulse on the low fet coincident
with
the turn on of the high fet- PCB is layed out to full guidelines from
harris
including laying gate traces with source feed on underside as plane to
reduce the chance of this phenomina-

any usefull ideas on reducing this- unit works well but this is obviously
wasting power and heating the low side fet (although even without sink its
mostly cold)

Regards

Anthony C Smith

If the little pulses are large enough to cause dV/dt induced cross
conduction (have you actually measured the cross conducting current, or have
you merely observed small less than threshold blips appearing on the low
side MOSFET gates?), then there are a number of things you might try.

This document:

http://focus.ti.com/lit/ml/slup169/slup169.pdf

Would have you believe the gate resistor paralleled with diode only provides
incremental improvement over just the gate resistor alone (see figure 12 and
related text in the document). From my personal experience with dV/dt
induced cross conduction I would tend to agree. The document claims the
circuit of figure 13 is superior. I tend to agree, but I think the best
solution would be if MOSFET gate driver IC manufacturers provided two
separate pins for each gate drive output. One pin for sinking current and
one pin for sourcing current. That way you could use separate valued gate
drive resistors for sinking and sourcing. It seems in most power MOSFET
applications (especially true in H-bridges) turn on should be a fair amount
slower than turn off for optimal performance.

In addition to trying the circuitry of figure 13 you might also consider
applying negative gate drive, or perhaps keeping the same circuit you are
currently using (gate resistor in parallel with diode) but increasing the
upper MOSFETs' gate resistor values. If cross conduction really is
occurring, this can sometimes dramatically reduce total MOSFET heating even
though it makes turn on slower. Of course, this isn't optimal from a
performance standpoint since you probably want really fast turn on and turn
off without any dV/dt induced cross conduction, but sometimes the added gate
drive complexity may not be worth it (especially since fast turn on/off
worsens the EMI situation).

 

[Anthony C Smith]

-snip-

I doubt that's your problem, not if you were to use Schottky pulldown
diodes to control the off FET's anyway. Did you provide a delay using
the '4081 HDEL and LDEL resistors (pins 8, 9) to prevent shoot-through?

Using 68K for HDEL and LDEL- using the DSO I can see the delay so this is

not the problem- I also increased the values to no avail- I am trying the
diodes now
Regards
Anthony

Thanks,
- Win

 

[Winfield Hill]

Anthony C Smith wrote...

No I have measured the current -5ns 50A flowing...

How did you make this measurement (keep in mind L dI/dt)?


--
Thanks,
- Win

 

[Anthony C Smith]

"Winfield Hill" <hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote in
message news:cov11702253@drn.newsguy.com...

Anthony C Smith wrote...

No I have measured the current -5ns 50A flowing...

How did you make this measurement (keep in mind L dI/dt)?

It measures as a 0.75V peak pulse across a 0R015 non inductive sense
resistor between the bottom of the bridge and true ground- both paths are
less than 5mm long and over 5mm wide to avoid skin effect problems
regards
Anthony

 

[legg]

On Mon, 6 Dec 2004 09:22:18 +0000 (UTC), "Anthony C Smith"
<acs@mapsoncurrent-thinking.com> wrote:

So the basic idea is it is difficult to actually measure the cross
conduction current with any reasonable expectations of accuracy. By the
sounds of it you probably are getting cross conduction, but it is probably
not as severe as you think it is.
Thanks for the explaination- I am trying to fix a problem on a current board
any patch ideas? this is driving me up the wall- I was trying to lower the
THD and this spike is everywhere to some extent

You could increase the upper fet gate current turn-on limiter. You
obviously have incremental values to play with before you hit the same
value used on the lower part.

You haven't yet indicated whether the use of schottkies did anything
to your measurements.

RL

 

[Anthony C Smith]

"Terry Given" <my_name@ieee.org> wrote in message
news:sqXsd.22844$9A.395564@news.xtra.co.nz...

Hi Anthony,

A perhaps stupid question - is what you are seeing actually gate
current? If possible, re-route the lower FET gatedrive such that gate
charge and discharge current does not flow thru the sense resistor (easy
to do if you have a separate power gnd on the smps chip, or a transistor
buffer).

Its definately secondary turn on, albiet maybe smaller than I first thought
the above is not realy practical as its not a smps, its a discreet modulator
driving the HIP for an audio amplifier and the sense resistor is part of the
I limit system.
regards

 

[Anthony C Smith]

"legg" <legg@nospam.magma.ca> wrote in message
news:5gi8r0t8dhk2i0vld48tgmo4dmcc0gtt6u@4ax.com...

On Mon, 6 Dec 2004 09:22:18 +0000 (UTC), "Anthony C Smith"
acs@mapsoncurrent-thinking.com> wrote:


You could increase the upper fet gate current turn-on limiter. You
obviously have incremental values to play with before you hit the same
value used on the lower part.

I have been trying this and it appears to be working

You haven't yet indicated whether the use of schottkies did anything
to your measurements.

Strangely they did not improve things
thanks for the input

 

[legg]

On Mon, 6 Dec 2004 15:19:58 +0000 (UTC), "Anthony C Smith"
<acs@mapsoncurrent-thinking.com> wrote:

"Winfield Hill" <hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote in
message news:cp1j7m0fbb@drn.newsguy.com...
It's not clear Anthony is seeing shoot-through currents; there are many
other sources of impulse noise during switching that may be visible at
the FET's source lead. For example, the high capacitive gate currents
go through that path. One insidious severe noise source comes from fast
current snap-off in the FET's substrate diode after its reverse-recovery
time is finished. The primary way to tell this is happening is presence
of severe switching noise. This situation will arise whenever the FET
is off and its diode is made to conduct, say caused by flyback from the
inductance in Anthony's output filter, "H bridge drives a 40u common mode
choke followed by a 3rd order Butterworth filter at 50kHz."
I think I am getting to the problem- not quite where I thought it was,
the bridge is a phase shift type, with 0V in both bridges have a common mode
switching frequency, and switch together, +v one bridge duty cycle
increases, the other decreases,-v the opposite.
By removing the load and applying a DC offset it appears that the pulse is
comming from the oposite bridge half, and appears to be from the half under
measurement when at 0V or small signal input.

Whoa. You are driving a common-mode choke with a phase-modulated H
bridge? The common mode fundamental output component of a phase
modulator is extremely large.

Are you sure you are not driving your sources and drains above and
below their power rails? Is current really zero before the second
conduction event?

RL

 

[legg]

On Tue, 7 Dec 2004 05:06:38 +0000 (UTC), "Anthony C Smith"
<acs@mapsoncurrentthinking.coom> wrote:

"legg" <legg@nospam.magma.ca> wrote in message
news:1mf9r05bvscegm753u2pu5pu8klkmcup3m@4ax.com...
On Mon, 6 Dec 2004 15:19:58 +0000 (UTC), "Anthony C Smith"
acs@mapsoncurrent-thinking.com> wrote:

Whoa. You are driving a common-mode choke with a phase-modulated H
bridge? The common mode fundamental output component of a phase
modulator is extremely large.

The choke removes most of the common mode component, the following filter
then only works on the diffential signal.
Are you sure you are not driving your sources and drains above and
below their power rails? Is current really zero before the second
conduction event?
There is currently a 3V overshoot on the bridge output, no undershoot (or
negligable) and all four devices are snubbed with 10R/1n, as well as the cm
choke to reduce ringing. from the data the devices should cope with this
easily-or am I missing something?

scaling of CM Choke- I have scaled the current for the choke at 10A (I need
7A through the choke to drive the audio) as the common mode signal should
result in no net ampere turns does anyone have any experiance with this?

Don't think construction of choke is an issue, depending on how much
leakage is intentionally present.

The voltage waveform will differ slightly on leading and lagging
phase, dependant on PWdelay and load.

If your measurements show zero current in the lower fet before the
second conduction event, then there's no issue there, either.

RL

 

[Anthony C Smith]

"Winfield Hill" <hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote in
message news:cp5dgp0lrj@drn.newsguy.com...

Anthony C Smith wrote...

To the contrary, it makes good sense. In fact I wrote you a message
from home this morning pointing out the issue, and suggesting you
move the CM-choke to _after_ the normal-mode filter (which should
be balanced and differential), or eliminating it entirely.

Removing the CM choke increases the current consumption as the filters
charge/discharge- wasting valuable battery time, using the CM choke means
the filters only work when audio is not at 0V (which it is most of the time!
The output filter first section is balanced, second section the caps are
ground referanced hence the charging- i needed to do this to help with
getting the noise down on previous boards to pass emc- might try
re-arranging the filter this weekend!

However before I could send the note, my computer crashed.

In fact it crashed so thoroughly a little Chinese voice came out
of my speaker, "system failure, CPU... system failure, CPU...
system failure, CPU... system failure, CPU..." Now the computer
fails reboot attempts, or anything. I'll probably be out another
$300 for a new Pentium 4 chip. It's OK, I'll send you the bill...
I mean it's only fair, your note broke it.

this has helped the design no end, THD has plummeted to 0.01%
@10KHz -10dB not bad for battery backed voice amplifier!!

On a different note- does anyone have any sneaky circuits for
stopping the error amp output exceeding the ramp- Zeners are slow
and act two early- I have used a complimentary pair of transistors
with the bases dc biased to the ramp peaks less 200mV and a pair
of 1n4148 to remove current from the error amplifier- this is fast
and scales well with supply rails- but can't help thinking there
is a more elegant way.

Tell us more about that there error amplifier. What is it?

the H bridge output is RC filtered and "de-balanced" before passing into an

inverting op amp node- input is cap coupled 3k3 resistor, feedback is 10k
(from debalancer to node), node is compensated with 4k7/47p in series-
op amp is TS462 from SGS and operates single supply 12V (swings0.3V to
11.6V) but the ramp only has 10V swing- derived from a xtal and passed thru
integrator- gives an excellently symetrical triangle- most important for low
THD


regards
Anthony

 

[Winfield Hill]

Terry Given wrote...

Winfield Hill wrote:
... To measure differential voltages, such as the floating Vgs
for the high-side FETs, or the H-bridge output, I use differential
probes; either handmade, or a LeCroy / Preamble amplified wideband
probe. With a 500MHz digital scope. That's what it takes to get
the T-shirt.

Care to elaborate on the home-made differential probes?

Well, maybe I should say matched pair with common ground. This is a
poor man's probe that works surprisingly well in difficult scenes.

.. scope RG-174 50-ohm coax
.. ____________________/
.. (O)____________________)-950R--->
.. w/ 50-ohm |__________ local gnd.
.. term ____________________|
.. (O)____________________)-950R--->

Both scope channels have internal wideband 50-ohm terminations. So
the end of the coax looks like a 50-ohm load to the matched 950-ohm
axial-lead resistors, resulting in a pair of matched 20:1 attenuators.
Or use 50-ohm resistors for 10:1 attenuation. The coax transmission
line serves to isolate the local probed ground from the scope ground.
And most power and high-frequency circuitry doesn't mind a 500 or 1k
probing load.

But I still prefer my Tektronix, HP and LeCroy differential probes.

Also: trying to measure small Vds_on voltages when Vds_off is very
large doestn work well - when the scope is set to small V/div it gets
grossly over-driven by Vds_off. This causes thermal tails, which can
take a long time to settle out, and can do a great job of corrupting
the small-amplitude measurement just attempted.

Get a better scope (mine doesn't do that). Or use an external fast
clamp circuit to protect the scope from far-out-of-range signals.

IIRC linear tech AN47 covers this in some detail, along with a great
tute on scope probing.

Yes. Jim shows my resistor-coax-probe trick, page 80.


--
Thanks,
- Win