Second argument of write must have a constant value.

[Nikola Skoric]

Hello there,

I'm rather new to VHDL and find this piece of code perfectly legitimate:

architecture Behavioral of writer is
file FP: TEXT open write_mode is "output.txt";
begin
process (write) is
variable l : line;
variable data : std_logic_vector(63 downto 0);
begin
if (rising_edge(write)) then
data := DATA_in;
write(l,data);
writeline(FP,l);
end if;
end process;

end Behavioral;

But my analyzer disagrees, and says: "Second argument of write must have
a constant value." What should I do to please my analyzer?

--
"Now the storm has passed over me
I'm left to drift on a dead calm sea
And watch her forever through the cracks in the beams
Nailed across the doorways of the bedrooms of my dreams"

 

[Colin Marquardt]

Nikola Skoric <nick-news@net4u.hr> writes:

I'm rather new to VHDL and find this piece of code perfectly legitimate:
[...]
process (write) is

I wouldn't reuse that function name for a signal.

Cheers,
Colin

 

I'm guessing that you're using textio:

write(L, VALUE, JUSTIFY, FIELD); -- Write one value to "line" L from
variable VALUE
* Data_type of VALUE can be bit, bit_vector, integer, real,
character, string, or time.
* JUSTIFY is "left" or "right" to justify within the field
* FIELD is the desired field width of the written value


You must convert the value from std_logic_vector to bit_vector before
write will accept it.

 

[Nikola Skoric]

In article <1150328969.497703.250420@h76g2000cwa.googlegroups.com>,
ghelbig@lycos.com says...

I'm guessing that you're using textio:

write(L, VALUE, JUSTIFY, FIELD); -- Write one value to "line" L from
variable VALUE
* Data_type of VALUE can be bit, bit_vector, integer, real,
character, string, or time.
* JUSTIFY is "left" or "right" to justify within the field
* FIELD is the desired field width of the written value


You must convert the value from std_logic_vector to bit_vector before
write will accept it.

Oh, right. Thanks. Works now.

While we're at it, can you recommend me some kind of VHDL reference? For
instance, this code I've written dumps a series of bits to the file...
and now I'd like to convert that bit_vector to string containing hex
digits. Where do I start seraching for such a function?

--
"Now the storm has passed over me
I'm left to drift on a dead calm sea
And watch her forever through the cracks in the beams
Nailed across the doorways of the bedrooms of my dreams"

 

[Colin Marquardt]

Nikola Skoric <nick-news@net4u.hr> writes:

and now I'd like to convert that bit_vector to string containing hex
digits. Where do I start seraching for such a function?

Check out image_pb.vhd on
http://members.aol.com/vhdlcohen/vhdl/Models.html, or the packages
on http://bear.ces.cwru.edu/vhdl/

Cheers,
Colin