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HiHi, newgrouper,
does anyone know what dqm does ? The specification of micron is
vague. What mask function does it mean ?
Thanks
Steven.
That is part of it. In essence the DQM is a byte enable. On write itSteven wrote:
Hi, newgrouper,
does anyone know what dqm does ? The specification of micron is
vague. What mask function does it mean ?
Thanks
Steven.
Hi
My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address.
A little example:
If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables.
Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable.
If I'm wrong I'm sure someone will correct me.
I checked a datasheet picked at random from Micron (MT16VDDT3264A) and there it says that DM (the name for dqm in the data sheet) only affects the write operation. I have not checked to many other datasheets, my feeling is that this is the standard way.user@domain.invalid wrote:
Steven wrote:
Hi, newgrouper,
does anyone know what dqm does ? The specification of micron is
vague. What mask function does it mean ?
Thanks
Steven.
Hi
My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address.
A little example:
If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables.
Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable.
If I'm wrong I'm sure someone will correct me.
That is part of it. In essence the DQM is a byte enable. On write it
will allow or prevent the write on a byte by byte basis. On read, IIRC,
it will enable the data output or tristate the output on byte by byte
basis.
My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address.
A little example:
If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables.
Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable.
If I'm wrong I'm sure someone will correct me.
That is part of it. In essence the DQM is a byte enable. On write it
will allow or prevent the write on a byte by byte basis. On read, IIRC,
it will enable the data output or tristate the output on byte by byte
basis.
I am a bit confused what you are really asking about. Try to define the following and it might be easier for someone to help you:My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address.
A little example:
If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables.
Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable.
If I'm wrong I'm sure someone will correct me.
That is part of it. In essence the DQM is a byte enable. On write it
will allow or prevent the write on a byte by byte basis. On read, IIRC,
it will enable the data output or tristate the output on byte by byte
basis.
what does enable mean here ? In Write, DQM is high when it receives data?
I have simulated testbench from micron, the DQM doesnot change.
Thanks
Steven
The above quote is what I remembered about DQM. It is a mask or a byteexcuse me, Fredrik, I have thought the interface of sdram is almost
same from different manufacturers, it seems not so true.
I am now doing a sdram controller design for a special processor
architecture
The Ram I targets is Micron's sdram MT48LC16M16A2TG, which has 256mb
capacity.
Here is the address of it.
http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A
The signal dqm causes me much wonder. The datasheets says:
--- quote ---
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered
same state when referenced as DQM.
-- quote end -----
DQM is input signal, which I falsely thought is output in the first
message. Is mask means that I can overwrite just part of address, say
1 byte from 2 bytes cell? This is what was suggested by the above
msgs. But what is dqm function in read, what means "an output enable
signal for read accesses."
I think it is a very sound and useful observation that one should not assume that all sdram work the same, even if they are supposed to, always read the data sheet. In an earlier post I picked a data-sheet at random, but it was actually a DDR-SDRAM.Steven wrote:
excuse me, Fredrik, I have thought the interface of sdram is almost same from different manufacturers, it seems not so true.
I am now doing a sdram controller design for a special processor architecture The Ram I targets is Micron's sdram MT48LC16M16A2TG, which has 256mb capacity.
Here is the address of it. http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A
The signal dqm causes me much wonder. The datasheets says:
--- quote --- Input/Output Mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM.
-- quote end -----
DQM is input signal, which I falsely thought is output in the first message. Is mask means that I can overwrite just part of address, say 1 byte from 2 bytes cell? This is what was suggested by the above msgs. But what is dqm function in read, what
means "an output enable signal for read accesses."
The above quote is what I remembered about DQM. It is a mask or a byte enable for writing and an output enable for reading. There will be a separate DQM input signal for each byte in the SDRAM.
In read the output of a byte that is not enabled is held tri-state (Hi-Z). Bytes that are enabled will output data onto the data bus.
If you don't need independant byte access, you can just tie all DQM signals low and the chip will always read or write the full word of data.
Of course it should ignore the data signals that are disabled.rickman wrote:
Steven wrote:
excuse me, Fredrik, I have thought the interface of sdram is almost
same from different manufacturers, it seems not so true.
I am now doing a sdram controller design for a special processor
architecture The Ram I targets is Micron's sdram MT48LC16M16A2TG, which
has 256mb capacity.
Here is the address of it.
http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A
The signal dqm causes me much wonder. The datasheets says:
--- quote --- Input/Output Mask: DQM is an input mask signal for
write accesses and an output enable signal for read accesses. Input data
is masked when DQM is sampled HIGH during a WRITE cycle. The output
buffers are placed in a High-Z state
(two-clock latency) when DQM is sampled HIGH during a READ cycle. On
the x16, DQML corresponds to DQ0-DQ7 and DQMH corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
-- quote end -----
DQM is input signal, which I falsely thought is output in the first
message. Is mask means that I can overwrite just part of address, say 1
byte from 2 bytes cell? This is what was suggested by the above msgs.
But what is dqm function in read, what
means "an output enable signal for read accesses."
The above quote is what I remembered about DQM. It is a mask or a
byte enable for writing and an output enable for reading. There will be
a separate DQM input signal for each byte in the SDRAM.
In read the output of a byte that is not enabled is held tri-state
(Hi-Z). Bytes that are enabled will output data onto the data bus.
If you don't need independant byte access, you can just tie all DQM
signals low and the chip will always read or write the full word of data.
I think it is a very sound and useful observation that one should not
assume that all sdram work the same, even if they are supposed to,
always read the data sheet. In an earlier post I picked a data-sheet at
random, but it was actually a DDR-SDRAM.
Rick gave a good explanation on the "enable question", I will just make
personal expounding why I would not make use of it in a READ access to
the SDRAM.
Even if the data output from the SDRAM are tri-stated, there are
actually some voltage level on the signal between the SDRAM and the FPGA
but not known. It could be below 0.8V (ensured as a logic 0), above 2V
(ensured as logic 1) or somewhere between. This make it necessary to
implement the SDRAM-controller to ignore the inputs on the signal that
are enabled (mask it). Another thing is that the probability that the
voltage is between 0.8V and 2V is much higher. You should review your
design to ensure that it is robust against meta-stability during the
READ. Another argument is that you can save some logic by always having
dqm '0' during a read, you must implement the "masking" in the
controller anyway.
The above reasoning is for connecting only one SDRAM to one controller.
One can maybe think of more complex scheemes e.g. several SDRAMS that
are read bytewise simultaniously by the same controller. Then
tri-stating the drivers are a must.
I guess this was a bit out of scope.
/Pfna