SDRAM

R

RANGA REDDY

Guest
Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the code
for Fujitsu SDRAM specifications.

Anybody can help in this regard please reply to
sudharr@myw.ltindia.com .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,

S.RANGA REDDY
 
a
sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0405252227.77dfb1f2@posting.google.com>...
Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the code
for Fujitsu SDRAM specifications.

Anybody can help in this regard please reply to
sudharr@myw.ltindia.com .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,

S.RANGA REDDY
Click to expand...
 
I think, you just send auto refresh command to sdram, and set a count,
let it count down from the cycles it needs. When count equals 0, then
auto refresh is finished. SDRAM does the job automatically.


Steven



sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0405252227.77dfb1f2@posting.google.com>...
Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the code
for Fujitsu SDRAM specifications.

Anybody can help in this regard please reply to
sudharr@myw.ltindia.com .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,

S.RANGA REDDY
Click to expand...
 
Hi

is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

please reply me answer..

regards,

S.RANGA REDDY



dxslyz@lycos.de (Steven) wrote in message news:<bcbfc047.0405260919.70a46cbb@posting.google.com>...
I think, you just send auto refresh command to sdram, and set a count,
let it count down from the cycles it needs. When count equals 0, then
auto refresh is finished. SDRAM does the job automatically.


Steven



sudharr@myw.ltindia.com (RANGA REDDY) wrote in message news:<37ba429a.0405252227.77dfb1f2@posting.google.com>...
Hi all,

can anybody tell how autorefresh in SDRAM exactly works? suppose in
SDRAM specifications it is mentioned that 64 ms, 4096 cycle
refresh(15.6 us/row) what exactly it means and how we need to generate
the autorefresh cycles.

actually i am trying to upgrade the 512k*4*32 SDRAM(Fujitsu Make) to
Micron Make 1M*4*32 SDRAM.

FUJITSU specifies that 4K refresh cycles every 16ms, auto refresh (3.9
us) and micron specifies that 64 ms, 4096 cycle refresh(15.6 us/row).

Did any body tried to do this kind of upgradation. we have the code
for Fujitsu SDRAM specifications.

Anybody can help in this regard please reply to
sudharr@myw.ltindia.com .i can send u the data sheets of both the
SDRAMs,if you want.

thanks and regards,

S.RANGA REDDY
Click to expand...
 
RANGA REDDY wrote:
is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?
Click to expand...
AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
are touched (read or written) sufficiently often. I think once every
64ms is enough.

I've never seen anybody take advantage of that though.

Tommy
 
Tommy Thorn wrote:
RANGA REDDY wrote:
is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
are touched (read or written) sufficiently often. I think once every
64ms is enough.

I've never seen anybody take advantage of that though.
Click to expand...
There are some apps where the refresh is done automatically by the
repetitive accesses, like video for example. The refresh period varies
with different row/column sizes and layout, so check the data sheet! I
recall that the older parts were in the low ms range, but the period
increased as the number of rows increased.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
[DRAM refresh not needed if you read/write often enough]

I've never seen anybody take advantage of that though.
Click to expand...
We built a delay line using DRAM. The idea was to simulate
a 10,000 km 155 megabit link in order to test software.

No refresh needed. Just assign the RAS/CAS bits such that
you use each row often enough. On the other hand, you can
save power if you don't touch rows more often than necessary.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
hmurray@suespammers.org (Hal Murray) wrote in message news:<z8OdnaZ9j5PaGFfd4p2dnA@megapath.net>...
I've never seen anybody take advantage of that though.

We built a delay line using DRAM. The idea was to simulate
a 10,000 km 155 megabit link in order to test software.

No refresh needed. Just assign the RAS/CAS bits such that
you use each row often enough. On the other hand, you can
save power if you don't touch rows more often than necessary.
Click to expand...
Curious, I am planning on making my cpu DDR interface run as hot as
possible (not that I like heat) but I am running no sram data cache
since the ld/st address for 16 threads will be more random than a
small cache could handle.

The DDR specs I have from Micron are vague on power dissipation or I
haven't found it yet for the case I am interested in.

In order to allow so many threads I also need to thow them around to
different banks, if they all hog 1 bank, perf would be impacted.

So how much power can a typ 256M DDR DRAM dissipate when running
Ras/Cas cycles as often as possible at say 250MHz and on random banks
1 or 2 simultaneous?

regards

johnjakson_usa_com
 
The DDR specs I have from Micron are vague on power dissipation or I
haven't found it yet for the case I am interested in.
Click to expand...
There is probably a section on current used under various
conditions.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
 
Tommy Thorn <TommyAtNumba-Tu.Com--not@yahoo.com> writes:

RANGA REDDY wrote:
is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

AFAIK, *no* SDRAM requires refresh cycles if all the rows you care
about are touched (read or written) sufficiently often. I think once
every 64ms is enough.

I've never seen anybody take advantage of that though.
Click to expand...
Our video-processing app doesn't bother with refresh for the display
frame buffer.

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt
 
A read on a row in SDRAM accomplishes a refresh, so if you read all used
rows within the refresh period, you do not need an explicit refresh. I've
used that in video applications on several occasions.

Tommy Thorn wrote:

RANGA REDDY wrote:
is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
are touched (read or written) sufficiently often. I think once every
64ms is enough.

I've never seen anybody take advantage of that though.

Tommy
Click to expand...
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
 
In article <40C9D4DC.8060900@yahoo.com>, TommyAtNumba-Tu.Com--
not@yahoo.com says...
RANGA REDDY wrote:
is it true that Micron SDRAM does not require any refresh cycles if we
are reading the SDRAM rows once in 20 ms atleast? if i dont give any
refresh cycles what will be the condition of the SDRAM?

AFAIK, *no* SDRAM requires refresh cycles if all the rows you care about
are touched (read or written) sufficiently often. I think once every
64ms is enough.

I've never seen anybody take advantage of that though.
Click to expand...
The original IBM PC had one of the DMA channels set up to do periodic
reads from contiguous locations to the DRAM refresh.

--
Keith
 
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