SDRAM-Controller XAPP134

[Simone Winkler]

Hello!

Is anyone of you familiar with the Xilinx Application Note XAPP134?
(downloadable at http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf ,
ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip)

My questions are:
* From the system, you can control the SDRAM with commands that are defined
through data_addr_n, we_rn and AD[29:28].
When I set one command, does it have to be set back to zero afterwards and
when?
E.g. when I write, I first set the addr_wr command and the address, then the
data_wr command and the data, but afterwards, do I have to set everything
(including the AD-bus) back to zero? (because, also zeros stand for a
command).

* I am wondering what I have to do at the very beginning:
At first, I put a reset, and it takes some time until I can perform any
action.
Then I precharge and load the controller mode register (this has to be done
before anything else can be done, right?)
But then....? Do I have to load the SDRAM mode register before I can
read/write/auto refresh/...

* And did I understand right, that I still have to do the refresh by hand,
so every 64ms? By issueing the command AUTO REFRESH? Or does the controller
already do this for me?

* But now, finally the last question:
In the future, I need a 16-bit-wide-data-bus-design for a 32mb module
instead of the 32-bit-design that is given here. The data destination should
then be masked by the DQMs. How can I easily convert this?

Thank you VERY MUCH!

Simone Winkler

 

[Swarna Kumar]

I am using ISE 6.1i, I have also installed the 6.1i service pack. <BR>
I am getting the following error when I am trying to synthesize one of my designs. <p>FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at <a href="http://support.xilinx.com">http://support.xilinx.com</a>. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at <a href="http://support.xilinx.com">http://support.xilinx.com</a> <p>What do I do? <p>Swarna

 

[rickman]

Simone Winkler wrote:

Hello!

Is anyone of you familiar with the Xilinx Application Note XAPP134?
(downloadable at http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf ,
ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip)

My questions are:
* From the system, you can control the SDRAM with commands that are defined
through data_addr_n, we_rn and AD[29:28].
When I set one command, does it have to be set back to zero afterwards and
when?
E.g. when I write, I first set the addr_wr command and the address, then the
data_wr command and the data, but afterwards, do I have to set everything
(including the AD-bus) back to zero? (because, also zeros stand for a
command).

Well, the answer is yes and no. All command lines at zero is a command,
but it is a NOP command. That is what you send when you don't have any
other command to send. Timing is very important on SDRAMs. There are
clock cycle timings such as setup and hold, but there are also timings
that affect how many clock cycles you have to wait between commands.
Read the spec sheet very carefully.

IIRC, one command line (perhaps CS) can be set to zero regardless of
what the others are doing and this is a NOP as well.

* I am wondering what I have to do at the very beginning:
At first, I put a reset, and it takes some time until I can perform any
action.
Then I precharge and load the controller mode register (this has to be done
before anything else can be done, right?)
But then....? Do I have to load the SDRAM mode register before I can
read/write/auto refresh/...

There are a very specific set of operations you must do at startup.
Again all this is spelled out in the data sheet. There are differences
between manufacturers, but according to the data I read when I did my
design (some 5 years ago...) there is a subset (or is it superset?) that
will work with most if not all. Micron used to have a very clear app
note on initialization.

* And did I understand right, that I still have to do the refresh by hand,
so every 64ms? By issueing the command AUTO REFRESH? Or does the controller
already do this for me?

Hmmmm. Now you are testing my memory. I think you have to tell the
chip when to do a refresh, but you don't have to provide an address
since an internal counter does that for you.

* But now, finally the last question:
In the future, I need a 16-bit-wide-data-bus-design for a 32mb module
instead of the 32-bit-design that is given here. The data destination should
then be masked by the DQMs. How can I easily convert this?

If I were you, I would use the DQMs to mask writes (which is what I
think they are for) and aren't there byte enables as well for the
reads? If so, you can tie the two 16 halves together to form one 16 bit
bus and alternate enables on page boundaries. It would seem to me if
you try to alternate enables on each word, the burst feature can not be
used.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[Simone Winkler]

"rickman" &lt;spamgoeshere4@yahoo.com&gt; schrieb im Newsbeitrag

: Well, the answer is yes and no. All command lines at zero is a command,
: but it is a NOP command. That is what you send when you don't have any
: other command to send. Timing is very important on SDRAMs. There are
: clock cycle timings such as setup and hold, but there are also timings
: that affect how many clock cycles you have to wait between commands.
: Read the spec sheet very carefully.
:
: IIRC, one command line (perhaps CS) can be set to zero regardless of
: what the others are doing and this is a NOP as well.
:

Yes - I read the spec of the SDRAM. But in the Xilinx Application Note
there's a design of a SDRAM controller that does a lot of things for me. I
just tell the controller by 4 signals (data_addr_n, we_rn, AD[29:28]) which
operation I want to do (PRECHARGE+LOAD CONTROLLER MODE REGISTER, AUTO
REFRESH, LOAD SDRAM MODE REGISTER, WRITE, READ). In the end, this controller
produces the CAS, RAS, WE,... signals for me.
So my question is about the control signals of the controller: all the
possible combinations of the control signals (data_addr_n, we_rn, AD[29:28])
exist, I don't know if i have to reset them in a special manner after I
perform any operation (PRECHARGE+LOAD CONTROLLER MODE REGISTER, AUTO
REFRESH, LOAD SDRAM MODE REGISTER, WRITE, READ).

: There are a very specific set of operations you must do at startup.
: Again all this is spelled out in the data sheet. There are differences
: between manufacturers, but according to the data I read when I did my
: design (some 5 years ago...) there is a subset (or is it superset?) that
: will work with most if not all. Micron used to have a very clear app
: note on initialization.
:
Again I read the specification. But also this is done by the controller
that Xilinx designed in its XAPP134.
When you do a PRECHARGE command, also the LOAD CONTROLLER MODE REGISTER
command is done. I think i still have got to load the SDRAM MODE REGISTER
(also a command that you can tell to the controller), but i'm not sure.

: Hmmmm. Now you are testing my memory. I think you have to tell the
: chip when to do a refresh, but you don't have to provide an address
: since an internal counter does that for you.

Yes...I think that's it. But I am not sure if the Xilinx Controller already
does refreshing for me (so that I never have to refresh), because there
exists a refresh counter in the Controller Mode register.


I'm sorry that I ask so many questions - but the documentation of the Xilinx
SDRAM is not too long - I miss a lot of things there, and I need to know the
exact interfacing procedure for being able to apply it to my system.

Thank you very much!!

Simone

 

[Robert Sefton]

Simone -

My guess is that the "data_read" command is the idle state. If you
haven't issued a prior "addr_read" command then there will be no data
for you to read anyway. To be sure, though, you should create a simple
test bench and simulate it.

I agree that the XAPP134 documentation is poor, and the code is just as
cryptic. Have fun.

Robert

"Simone Winkler" &lt;simone.winkler@gmx.at&gt; wrote in message
news:1069227037.669594@news.liwest.at...

Hello!

Is anyone of you familiar with the Xilinx Application Note XAPP134?
(downloadable at http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf
,
ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip)

My questions are:
* From the system, you can control the SDRAM with commands that are
defined
through data_addr_n, we_rn and AD[29:28].
When I set one command, does it have to be set back to zero afterwards
and
when?
E.g. when I write, I first set the addr_wr command and the address,
then the
data_wr command and the data, but afterwards, do I have to set
everything
(including the AD-bus) back to zero? (because, also zeros stand for a
command).

* I am wondering what I have to do at the very beginning:
At first, I put a reset, and it takes some time until I can perform
any
action.
Then I precharge and load the controller mode register (this has to be
done
before anything else can be done, right?)
But then....? Do I have to load the SDRAM mode register before I can
read/write/auto refresh/...

* And did I understand right, that I still have to do the refresh by
hand,
so every 64ms? By issueing the command AUTO REFRESH? Or does the
controller
already do this for me?

* But now, finally the last question:
In the future, I need a 16-bit-wide-data-bus-design for a 32mb module
instead of the 32-bit-design that is given here. The data destination
should
then be masked by the DQMs. How can I easily convert this?

Thank you VERY MUCH!

Simone Winkler

 

[Martin Euredjian]

"Simone Winkler" wrote:

Yes - I read the spec of the SDRAM. But in the Xilinx Application Note
there's a design of a SDRAM controller that does a lot of things for me.

Consider writing your own SDRAM controller. It isn't all that difficult and
you'll know exactly what it is doing each and every step of the way.
Besides, you can customize it to deal with your particular needs.

Write a little state machine for each operation. They write a separate
state machine that would constitute the external command processor. Done
deal. Of course, this isn't the only way to do it. You could, for example,
implement look-ahead processing to pipeline commands or modify burst access
length based on what's coming. The challenge in high-performance SDRAM
designs (well, one challenge) is the minimization of wasted clock cycles.
Entering and exiting transactions costs clocks and this can be mitigated by
using pipelining, among other techniques.


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

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