Guest
Hi,
I have some full adder that I can't understand it's timing behaviour.
It's has 3 inputs: s,b, ci
and 2 outputs: s, co
in my case a="1" b="0" ci "1"-> "0"
s was changed in 0 timepoint (that isn't what I expected)
co was changed in 140ps (as was expected)
This is the SDF definition:
(CELL
(CELLTYPE "adfull_uhvt_1")
(INSTANCE
ftpe_top_fftpe_processing_unit_radix_processing_machine_radix8_d_i_6_mult_mul_24_35_cdnfadd_030_0)
(DELAY
(ABSOLUTE
(IOPATH ci co (134.500::139.400) (148.800::153.400))
(IOPATH (posedge ci) s (114.300::211.000) (131.300::187.500))
(IOPATH (negedge ci) s (110.200::207.900) (127.500::184.300))
....
)
)
After changing it to:
(CELL
(CELLTYPE "adfull_uhvt_1")
(INSTANCE
ftpe_top_fftpe_processing_unit_radix_processing_machine_radix8_d_i_6_mult_mul_24_35_cdnfadd_030_0)
(DELAY
(ABSOLUTE
(IOPATH ci co (134.500::139.400) (148.800::153.400))
(IOPATH ci s (114.300::211.000) (131.300::187.500))
...
)
)
The delay for s worked.
anyway, the original SDF file is the foirst description, and I want to
understand why this isn't working.
any idea?
I guess this can be a result of this specify block description:
adfull_uhvt_1.V :
if (( b == 1'b1 ) && ( ci == 1'b0 ) )
( a => s ) = ( tpd_a_s_b_EQ_1_AN_ci_EQ_0_rise ,
tpd_a_s_b_EQ_1_AN_ci_EQ_0_fall );
if (( b == 1'b0 ) && ( ci == 1'b0 ) )
( a => s ) = ( tpd_a_s_b_EQ_0_AN_ci_EQ_0_rise ,
tpd_a_s_b_EQ_0_AN_ci_EQ_0_fall );
if (( ci == 1'b0 ) && ( a == 1'b1 ) )
( b => s ) = ( tpd_b_s_ci_EQ_0_AN_a_EQ_1_rise ,
tpd_b_s_ci_EQ_0_AN_a_EQ_1_fall );
if (( ci == 1'b0 ) && ( a == 1'b0 ) )
( b => s ) = ( tpd_b_s_ci_EQ_0_AN_a_EQ_0_rise ,
tpd_b_s_ci_EQ_0_AN_a_EQ_0_fall );
if (( b == 1'b0 ) && ( a == 1'b1 ) )
( ci => s ) = ( tpd_ci_s_b_EQ_0_AN_a_EQ_1_rise ,
tpd_ci_s_b_EQ_0_AN_a_EQ_1_fall );
if (( b == 1'b0 ) && ( a == 1'b0 ) )
( ci => s ) = ( tpd_ci_s_b_EQ_0_AN_a_EQ_0_rise ,
tpd_ci_s_b_EQ_0_AN_a_EQ_0_fall );
( posedge a => ( co :s )) = ( tpd_posedge_a_TO_co_rise ,
tpd_posedge_a_TO_co_fall );
( negedge a => ( co :s )) = ( tpd_negedge_a_TO_co_rise ,
tpd_negedge_a_TO_co_fall );
( posedge b => ( co :s )) = ( tpd_posedge_b_TO_co_rise ,
tpd_posedge_b_TO_co_fall );
( negedge b => ( co : s )) = ( tpd_negedge_b_TO_co_rise ,
tpd_negedge_b_TO_co_fall );
( posedge ci => ( co : s )) = ( tpd_posedge_ci_TO_co_rise ,
tpd_posedge_ci_TO_co_fall );
( negedge ci => ( co : s )) = ( tpd_negedge_ci_TO_co_rise ,
tpd_negedge_ci_TO_co_fall );
( posedge a => ( s : s )) = ( tpd_posedge_a_TO_s_rise ,
tpd_posedge_a_TO_s_fall );
( negedge a => ( s : s )) = ( tpd_negedge_a_TO_s_rise ,
tpd_negedge_a_TO_s_fall );
( posedge b => ( s : s )) = ( tpd_posedge_b_TO_s_rise ,
tpd_posedge_b_TO_s_fall );
( negedge b => ( s : s )) = ( tpd_negedge_b_TO_s_rise ,
tpd_negedge_b_TO_s_fall );
( posedge ci => ( s : s )) = ( tpd_posedge_ci_TO_s_rise ,
tpd_posedge_ci_TO_s_fall );
( negedge ci => ( s : s )) = ( tpd_negedge_ci_TO_s_rise ,
tpd_negedge_ci_TO_s_fall );
but I don't know what is the meaning of this syntax.
Can somebody explain?....
Thanks,
Pazia
I have some full adder that I can't understand it's timing behaviour.
It's has 3 inputs: s,b, ci
and 2 outputs: s, co
in my case a="1" b="0" ci "1"-> "0"
s was changed in 0 timepoint (that isn't what I expected)
co was changed in 140ps (as was expected)
This is the SDF definition:
(CELL
(CELLTYPE "adfull_uhvt_1")
(INSTANCE
ftpe_top_fftpe_processing_unit_radix_processing_machine_radix8_d_i_6_mult_mul_24_35_cdnfadd_030_0)
(DELAY
(ABSOLUTE
(IOPATH ci co (134.500::139.400) (148.800::153.400))
(IOPATH (posedge ci) s (114.300::211.000) (131.300::187.500))
(IOPATH (negedge ci) s (110.200::207.900) (127.500::184.300))
....
)
)
After changing it to:
(CELL
(CELLTYPE "adfull_uhvt_1")
(INSTANCE
ftpe_top_fftpe_processing_unit_radix_processing_machine_radix8_d_i_6_mult_mul_24_35_cdnfadd_030_0)
(DELAY
(ABSOLUTE
(IOPATH ci co (134.500::139.400) (148.800::153.400))
(IOPATH ci s (114.300::211.000) (131.300::187.500))
...
)
)
The delay for s worked.
anyway, the original SDF file is the foirst description, and I want to
understand why this isn't working.
any idea?
I guess this can be a result of this specify block description:
adfull_uhvt_1.V :
if (( b == 1'b1 ) && ( ci == 1'b0 ) )
( a => s ) = ( tpd_a_s_b_EQ_1_AN_ci_EQ_0_rise ,
tpd_a_s_b_EQ_1_AN_ci_EQ_0_fall );
if (( b == 1'b0 ) && ( ci == 1'b0 ) )
( a => s ) = ( tpd_a_s_b_EQ_0_AN_ci_EQ_0_rise ,
tpd_a_s_b_EQ_0_AN_ci_EQ_0_fall );
if (( ci == 1'b0 ) && ( a == 1'b1 ) )
( b => s ) = ( tpd_b_s_ci_EQ_0_AN_a_EQ_1_rise ,
tpd_b_s_ci_EQ_0_AN_a_EQ_1_fall );
if (( ci == 1'b0 ) && ( a == 1'b0 ) )
( b => s ) = ( tpd_b_s_ci_EQ_0_AN_a_EQ_0_rise ,
tpd_b_s_ci_EQ_0_AN_a_EQ_0_fall );
if (( b == 1'b0 ) && ( a == 1'b1 ) )
( ci => s ) = ( tpd_ci_s_b_EQ_0_AN_a_EQ_1_rise ,
tpd_ci_s_b_EQ_0_AN_a_EQ_1_fall );
if (( b == 1'b0 ) && ( a == 1'b0 ) )
( ci => s ) = ( tpd_ci_s_b_EQ_0_AN_a_EQ_0_rise ,
tpd_ci_s_b_EQ_0_AN_a_EQ_0_fall );
( posedge a => ( co :s )) = ( tpd_posedge_a_TO_co_rise ,
tpd_posedge_a_TO_co_fall );
( negedge a => ( co :s )) = ( tpd_negedge_a_TO_co_rise ,
tpd_negedge_a_TO_co_fall );
( posedge b => ( co :s )) = ( tpd_posedge_b_TO_co_rise ,
tpd_posedge_b_TO_co_fall );
( negedge b => ( co : s )) = ( tpd_negedge_b_TO_co_rise ,
tpd_negedge_b_TO_co_fall );
( posedge ci => ( co : s )) = ( tpd_posedge_ci_TO_co_rise ,
tpd_posedge_ci_TO_co_fall );
( negedge ci => ( co : s )) = ( tpd_negedge_ci_TO_co_rise ,
tpd_negedge_ci_TO_co_fall );
( posedge a => ( s : s )) = ( tpd_posedge_a_TO_s_rise ,
tpd_posedge_a_TO_s_fall );
( negedge a => ( s : s )) = ( tpd_negedge_a_TO_s_rise ,
tpd_negedge_a_TO_s_fall );
( posedge b => ( s : s )) = ( tpd_posedge_b_TO_s_rise ,
tpd_posedge_b_TO_s_fall );
( negedge b => ( s : s )) = ( tpd_negedge_b_TO_s_rise ,
tpd_negedge_b_TO_s_fall );
( posedge ci => ( s : s )) = ( tpd_posedge_ci_TO_s_rise ,
tpd_posedge_ci_TO_s_fall );
( negedge ci => ( s : s )) = ( tpd_negedge_ci_TO_s_rise ,
tpd_negedge_ci_TO_s_fall );
but I don't know what is the meaning of this syntax.
Can somebody explain?....
Thanks,
Pazia