sdf generation primetime

K

kris

Guest
Hi,

If I generate an sdf file with design_analyzer or primetime
1) when I only import the .db library and the verilog gate level netlist
I get the same delays as when I do 1) + I read in the dspf parasitics file.

What do I do wrong?
Do I need to execute a commando after I do read_parasitics in primetime
or set_load in design_analyzer?

Is it necessary to define the clk and the delay on the in/output signals?

KRis
 
I found what was wrong.

"kris" <twofold@gmx.net> wrote in message
news:bvff38$vsc$1@daisy.noc.ucla.edu...
Hi,

If I generate an sdf file with design_analyzer or primetime
1) when I only import the .db library and the verilog gate level netlist
I get the same delays as when I do 1) + I read in the dspf parasitics
file.

What do I do wrong?
Do I need to execute a commando after I do read_parasitics in primetime
or set_load in design_analyzer?

Is it necessary to define the clk and the delay on the in/output signals?

KRis
 
"kris" <twofold@gmx.net> wrote in message
news:bvfi85$1s1$1@daisy.noc.ucla.edu...
I found what was wrong.

So what was it?
 

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