SDF Delay Annotation

[Deepu]

Hi All,

I have a question regarding the delay annotation in verilog
simulation.

SDF file content (example - only max numbers):

For cell type moduleA

Aboslute delay is mentioned as (IOPATH a_tmp b_tmp :650) :
750)) // timescale 'ps'


Netlist description (Example):

moduleA (a_tmp, b_tmp, c_tmp, d_tmp);

// only ports of concern
output b_tmp;
input a_tmp;

submodule submoduleA (.I1
(a_tmp), .O(b_tmp), .I2(net10), .I3(d_tmp), .VPWR(1'b1), .VGND(1'b0));

endmodule



Sub Module description (Example):

// timescale 'ns'

module submodule (O, I1, I2, I3, VPWR, VGND);

output O;
input I1, I2, I3;

inout VPWR, VGND;

wire net_0, net_1;

nor (strong0, strong1) #(0.1,0.1,0.1) (0.1,0.1,0.1) Inst1 (O, I1,
net_0);
nand (strong0, strong1) #(0.1,0.1,0.1) (0.1,0.1,0.1) Inst2 (net_1, I2,
I3);
not (strong0, strong1) #(0.1,0.1,0.1) (0.1,0.1,0.1) Inst3 (net_0,
net_1);

endmodule


When i run the simulation & check the delay between 'a_tmp' to 'b_tmp'
on moduleA level, i was expecting it to have only 0.65/0.75 as per the
SDF file but i noticed the delay to be around '0.68/0.78' (with 0.3ns
added from submodule)

Is this expected & what is the reason?


Thanks for the help..

 

[Cary R.]

Deepu wrote:

<snip>

When i run the simulation & check the delay between 'a_tmp' to 'b_tmp'
on moduleA level, i was expecting it to have only 0.65/0.75 as per the
SDF file but i noticed the delay to be around '0.68/0.78' (with 0.3ns
added from submodule)

In general the delay should be the larger of the specify path delay or
the sum of distributed delays, so for this case I would expect only the
specify based delays.

Can you generate and submit a complete running example that demonstrates
the problem. You are missing the top level specify block and the
timescales are ambiguous. You can likely strip out all the superfluous
stuff and keep the size manageable. There could be a problem in your
code that is causing this odd behavior.

I'll also comment that the numbers don't add up. You say you are seeing
an extra 0.3ns of delay, but it looks like the delays are different by
0.03ns. It's also odd that the input path you are showing only goes
through one gate so why is it getting 0.3ns added vs 0.1ns of extra delay.

With a complete working example it will be easier for someone to poke at
what exactly is going on, but I agree from what you describe I would
only expect the specify (SDF) delay. FYI a missing SDF delay does not
imply a delay of zero. It is truly a missing delay and the default from
the specify block should be used.

Thanks for the help..

I'm not certain how much this helped, but it's a start.

Cary