sdf annotated gate level sims (your advice required)

[Arturi]

Hello all,

I am writing a guideline for sdf annotated gate level sims. Many
times, this task is assigned to young engineers who might, because
lack of experience, overlook some of important aspects of it.

I would be interested if you guys can give me some piece of advice.
Some important points to be considered in this task.

I would love to hear the no-go flags as well. Things like:
Don't start your task before you actually inspected the data you will
be simulating. This can save you unnecessary debugging time...

Thanks in advance.

cheers

 

[Kim Enkovaara]

Arturi wrote:

I am writing a guideline for sdf annotated gate level sims. Many
times, this task is assigned to young engineers who might, because
lack of experience, overlook some of important aspects of it.

In my opinion gate level simulations are not for the inexperienced
designers. Usually they require much skills in debugging different
X-propagation and timing problems (reading synthesized structures
from netlist, comparing result to language standards,
comparing STA vs. simulation etc.)

Usually in a big chip there is at least one bug in the simulator
causing some timing errors etc. And those are really hard to
figure out.

I would be interested if you guys can give me some piece of advice.
Some important points to be considered in this task.

At least some points in my opinion are
* Try to use the same testbench as with RTL
* Think about the external timing in the TB-gate interface, this
is the most common place for errors in the beginning
* Get the SDF to load without errors and understand the warnings
* Try to get the clocking to work, even tough everything else goes to X
* Do first simulations without notifiers and timing check warning
messages, just try to get the design to work
* Slash all the X-propagation problems in this stage (memory contents,
odd reset schemes, odd startup sequences, bist, bisr etc.)
* Add timing error reporting
* Separate start related errors and errors during normal functionality
* Try to understand first timing problems in the normal functional side
* Many of the startup warnings are impossible to get rid of
just waive them to be ok after understanding them
* Try with notifiers, usually the design will expolde and it's not worth
to get it to work in this mode


--Kim