SDF and negative holds during simulation

[leon]

I have a verilog library that has 0 time associated with $setup and
$hold as they are just place holders. The SDF file has delays that
result in negative hold times (the .lib of these libraries have
negative times for hold..). So a signal could change before the edge
of the flop as long as it changes after the violation window and the
new value should not get latched in. However in my simulation with
ncverilog I see the new value getting through.
It is my understanding that SDF will override all delays in the veilog
library so I assume there must be some switch that will tell the
simulator that this not an actual violation of setup or hold and
should behave as desired. I have tried several switches with NC but I
still dont have the right behavior - anyone out there know how to make
this work in simulation.

 

leon wrote:

The SDF file has delays that
result in negative hold times (the .lib of these libraries have
negative times for hold..). So a signal could change before the edge
of the flop as long as it changes after the violation window and the
new value should not get latched in. However in my simulation with
ncverilog I see the new value getting through.

As I understand it, these hold times only affect whether the
timing checks report a timing violation. They do not affect
the behavior of the flip-flop model, which will continue to
behave the way it was written to behave.

Typically such models are written with zero setup and hold
times, i.e. they sample exactly at the clock edge. For typical
flops with positve setup and hold times, that will behave as
expected any time you do not have a violation, because it
is sampling within the valid window.

With a negative hold time, your model is not sampling
within the valid window of the actual device. You have to
modify the model to make it do so. Fortunately, there is
Verilog language support to make this more convenient.

The $setuphold timing check provides two extra optional
outputs that provide a delayed clock and data signal.
You can connect these to your flip-flop model instead
of the normal clock and data signals. They are delayed
in such a way that the delayed clock falls within the
correct sampling window for the setup and hold with
respect to the delayed data. In your case, it should
just delay the data by an amount between the setup
time and the absolute value of the negative hold time.