Schematics for ISCAS89 benchmarks

[Fazela]

Hi All,
I have synthesized verilog netlists of the ISCAS89 benchmarks. I was
wondering if there was a way to get the schematic view of these
circuits. I tried doing an "import verilog" but I dont have any
standard cell library or so. I am just using the default class.v and
class.lib for synthesis with Design Compiler.
Is there another way to get the schematics of these circuits?

Thanks,
Fazela

 

There is a cell library provided by Prof. Dong S. Ha from Virginia
Tech. It is free for research instituations. Synthesize your ISCAS
circuits using Design Analyzer (or Design Vision) and simply view the
design schematic. You may also use Cadence BuildGates for synthesis.

There is not much to enjoy from schematics though, plenty of lines and
gates crossing over each other.

You may want to try ITC99 benchmark circuits which are larger and more
representative.

Regards,

Hrh.