sampling 100kHz signal on microcontroller ?

[Adam S]

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.

How about I set output frequency to 100kHz, and sample at 999.9375Hz.
This will give aliasing at every N*999.9375Hz, where N is an integer
0,1,2.. And because the 100kHz signal is being generated by the
microcontroller , it will always be synchronized to the sampling.

So when N=100, then a 100kHz signal appears as 100000 - 100*999.9375Hz =
6.25Hz signal. Once the 6.25Hz sampled data is inside then its just a
matter of performing software quadrature demodulation to extract narrow
band phase/magnitude.

One issue concerning me is how functional the on board ADC sample and
hold circuit will be at 100kHz.
Whats involved building an external sample and hold circuit that can sit
before a relatively slow ADC ? Would I use parts like a CD4066 analog
switch, a storage capacitor and FET op-amp buffer ?

CD4066 leakage typical 100pA, giving sample hold droop of 0.45V/s. I've
read about charge injection of analog switches. When does this become an
issue ?



.------< trigger MCU
|
100kHz |
input ------ |\

-----|CD4066|-o----|+\
------ | | /-o---> ADC

| .-|-/ |
--- | |/ |
220pF --- |______|
|
GND

Adam

 

[john jardine]

"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.

How about I set output frequency to 100kHz, and sample at 999.9375Hz.
This will give aliasing at every N*999.9375Hz, where N is an integer
0,1,2.. And because the 100kHz signal is being generated by the
microcontroller , it will always be synchronized to the sampling.

So when N=100, then a 100kHz signal appears as 100000 - 100*999.9375Hz =
6.25Hz signal. Once the 6.25Hz sampled data is inside then its just a
matter of performing software quadrature demodulation to extract narrow
band phase/magnitude.

One issue concerning me is how functional the on board ADC sample and
hold circuit will be at 100kHz.
Whats involved building an external sample and hold circuit that can sit
before a relatively slow ADC ? Would I use parts like a CD4066 analog
switch, a storage capacitor and FET op-amp buffer ?

CD4066 leakage typical 100pA, giving sample hold droop of 0.45V/s. I've
read about charge injection of analog switches. When does this become an
issue ?



.------< trigger MCU
|
100kHz |
input ------ |\
-----|CD4066|-o----|+\
------ | | /-o---> ADC
| .-|-/ |
--- | |/ |
220pF --- |______|
|
GND

Adam

For similar vector recovery I went down the same route a couple of years ago
and found that (say) a PIC ADC has a *far far* better hold and sample action
than any discrete version using 4066's etc.
4066 charge injection become an annoying problem with signals down in the
<100mV area and depending on the particular circuit arrangement can also be
the cause of mystifying DC offsets and drift.

Tried also the subsampling method (ie mixer down conversion) to 20Hz but
zig-zagging across the 2 signal channels in turn, storing the samples in
memory and shifting a set down by one, to maintain phase balance. Problems
then turned up with noise. Could get no better final accuracy than the
original signal to noise ratio. Usual answer is to average N samples but at
my low I.F this became untenable.
Presently playing with a setup generating a clean test sine and then
multiplying up 4-8-16 times, using a phase locked loop (4046). The resulting
square wave outputs are thus coherent with the test signal frequency and
4,8, or 16 samples can be taken from the 2 (variable phase shift/voltage)
unknown signal channels, by means of 2 phase sensitive rectifiers, built
round a 4066 and 4 opamps. Each sampling 'phase' is fed to the PSR's in turn
by another 4066.
Benefit is that the sampling is now done at signal frequency where lots of
samples can be effectively averaged by the PSR's. The PSR's work as
'lock-in' amplifiers. Noise integrates towards zero. The discrete
electronics are now taking the workload, leaving the PIC etc to sample at
leisure a few DC voltages and then do some Sine/Cosine/ArcTan calcs etc.
Only 4 DC samples need taking (better yet if 8-16-32 etc), hence the
'discrete Fourier transform' can be used to accurately 'curve fit' a
correctly phased sine cycle, over the top of 4 pleasingly clean data points.
regards
john

 

[Adam S]

john jardine wrote:

"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.

How about I set output frequency to 100kHz, and sample at 999.9375Hz.
This will give aliasing at every N*999.9375Hz, where N is an integer
0,1,2.. And because the 100kHz signal is being generated by the
microcontroller , it will always be synchronized to the sampling.

So when N=100, then a 100kHz signal appears as 100000 - 100*999.9375Hz =
6.25Hz signal. Once the 6.25Hz sampled data is inside then its just a
matter of performing software quadrature demodulation to extract narrow
band phase/magnitude.

One issue concerning me is how functional the on board ADC sample and
hold circuit will be at 100kHz.
Whats involved building an external sample and hold circuit that can sit
before a relatively slow ADC ? Would I use parts like a CD4066 analog
switch, a storage capacitor and FET op-amp buffer ?

CD4066 leakage typical 100pA, giving sample hold droop of 0.45V/s. I've
read about charge injection of analog switches. When does this become an
issue ?



.------< trigger MCU
|
100kHz |
input ------ |\
-----|CD4066|-o----|+\
------ | | /-o---> ADC
| .-|-/ |
--- | |/ |
220pF --- |______|
|
GND

Adam



For similar vector recovery I went down the same route a couple of years ago
and found that (say) a PIC ADC has a *far far* better hold and sample action
than any discrete version using 4066's etc.
4066 charge injection become an annoying problem with signals down in the
100mV area and depending on the particular circuit arrangement can also be
the cause of mystifying DC offsets and drift.

Tried also the subsampling method (ie mixer down conversion) to 20Hz but
zig-zagging across the 2 signal channels in turn, storing the samples in
memory and shifting a set down by one, to maintain phase balance. Problems
then turned up with noise. Could get no better final accuracy than the
original signal to noise ratio. Usual answer is to average N samples but at
my low I.F this became untenable.
Presently playing with a setup generating a clean test sine and then
multiplying up 4-8-16 times, using a phase locked loop (4046). The resulting
square wave outputs are thus coherent with the test signal frequency and
4,8, or 16 samples can be taken from the 2 (variable phase shift/voltage)
unknown signal channels, by means of 2 phase sensitive rectifiers, built
round a 4066 and 4 opamps. Each sampling 'phase' is fed to the PSR's in turn
by another 4066.
Benefit is that the sampling is now done at signal frequency where lots of
samples can be effectively averaged by the PSR's. The PSR's work as
'lock-in' amplifiers. Noise integrates towards zero. The discrete
electronics are now taking the workload, leaving the PIC etc to sample at
leisure a few DC voltages and then do some Sine/Cosine/ArcTan calcs etc.
Only 4 DC samples need taking (better yet if 8-16-32 etc), hence the
'discrete Fourier transform' can be used to accurately 'curve fit' a
correctly phased sine cycle, over the top of 4 pleasingly clean data points.
regards
john

John, , I'm not quite familiar with the term subsampling, but I assume
this is the technique I described. i.e sample at lower rate and utilize
aliasing to access higher frequencies. I see now extra problems with
this method as it samples all superimposed bands spaced at intervals of
the sampling frequency. e.g if Fs=1kHz, and the input bandwidth is
200kHz, any noise from 0 to 200kHz will be superimposed on the sampled
data.

I am also not sure what a phase sensitive rectifier is. One idea that I
originally came up with is to multiply the two unknown input channels
each with a 0° and 90° signal. The resulting 4 outputs are averaged to
give DC values of complex and real and imaginary component sets( A+jB,
C+jD).

The ASCII schematic shown below is something what I was considering. The
inputs go to inverting amplifiers, where they are multiplied by either
+1 or -1, depending on the state of the 4053 analog switch. 2 of the
analog switches are driven at 90° to the other 2 switches, as shown on
the diagram. Since multiplication is effectively by a square wave there
will be some out of band noise occurring at odd harmonics. The
calculations needed to extract relative phase and magnitude are;

phase difference = atan((A-C)/(B-D))
magnitude ratio = sqrt( A*A + B*B)/(C*C +D*D) )



___
Channel 1 ,|___|--. .-----o--------.
| | 0° | | |
___ | |\ | phase --- | |\ |
o---o-|___|-'-|-\ | --- '---|-\ | A
| | >--o---o ___ | ___ | >-o-->
| GND -|+/ | o--|___|- -|___|-o-|+/
| |/ | .-o/ | |/
| | | (4053) ---
| | | ---
| | | |
'--------------- -o GND
| |
| | .-----o--------.
| | | | |
| | 90° --- | |\ |
| | phase --- '---|-\ | B
| '-o ___ | ___ | >-o-->
| o--|___|- -|___|-o-|+/
'---o/ | |/
(4053) ---
---
|
GND

___
Channel 2 ,|___|--. .-----o--------.
| | | | |
___ | |\ | 0° --- | |\ |
o---o-|___|-'-|-\ | phase --- '---|-\ | C
| | >--o---o ___ | ___ | >-o-->
| GND -|+/ | o--|___|- -|___|-o-|+/
| |/ | .-o/ | |/
| | | (4053) ---
| | | ---
| | | |
'--------------- -o GND
| |
| | .-----o--------.
| | | | |
| | 90° --- | |\ |
| | phase --- '---|-\ | D
| '-o ___ | ___ | >-o-->
| o--|___|- -|___|-o-|+/
'---o/ | |/
(4053) ---
---
|
GND

(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

 

[Ken Smith]

In article <42f1e3ee$0$25984$afc38c87@news.optusnet.com.au>,
Adam S <no@body.home.com> wrote:
[....]

How about I set output frequency to 100kHz, and sample at 999.9375Hz.
This will give aliasing at every N*999.9375Hz, where N is an integer
0,1,2.. And because the 100kHz signal is being generated by the
microcontroller , it will always be synchronized to the sampling.

Ideally, you want to sample faster than twice the bandwidth of the signal
you are dealing with. An active filter can fairly easily have a Q of 5 so
you would end up sampling at above 40KHz to get the best performance.

Even if you don't sample at at least 40KHz, the faster you sample the
better because there will be less aliasing.

[...]

.------< trigger MCU
|
100kHz |
input ------ |\
-----|CD4066|-o----|+\
------ | | /-o---> ADC
| .-|-/ |
--- | |/ |
220pF --- |______|
|
GND

Since it is an AC signal you are trying to produce at the output of the
sample and hold, you don't have to worry about the linear charge injection
effects since they just add a small offset and an even smaller gain error.

You will be better off using the extra hardware to mix down to a
lower frequency and applying a bandpass filter. This will greatly reduce
the aliasing problems.



--
--
kensmith@rahul.net forging knowledge

 

[John Larkin]

On Thu, 04 Aug 2005 19:46:22 +1000, Adam S <no@body.home.com> wrote:

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.

How about I set output frequency to 100kHz, and sample at 999.9375Hz.
This will give aliasing at every N*999.9375Hz, where N is an integer
0,1,2.. And because the 100kHz signal is being generated by the
microcontroller , it will always be synchronized to the sampling.

So when N=100, then a 100kHz signal appears as 100000 - 100*999.9375Hz =
6.25Hz signal. Once the 6.25Hz sampled data is inside then its just a
matter of performing software quadrature demodulation to extract narrow
band phase/magnitude.

One issue concerning me is how functional the on board ADC sample and
hold circuit will be at 100kHz.
Whats involved building an external sample and hold circuit that can sit
before a relatively slow ADC ? Would I use parts like a CD4066 analog
switch, a storage capacitor and FET op-amp buffer ?

CD4066 leakage typical 100pA, giving sample hold droop of 0.45V/s. I've
read about charge injection of analog switches. When does this become an
issue ?



.------< trigger MCU
|
100kHz |
input ------ |\
-----|CD4066|-o----|+\
------ | | /-o---> ADC
| .-|-/ |
--- | |/ |
220pF --- |______|
|
GND

Adam

I agree with JJ: the ADC in the uP is likely better than any s/h you
can easily build yourself.

Since the uP generates the 100K, why not take two sample sets, one
in-phase with the 100k and a second set delayed by 2.5 usec, 90
degrees. Take them in alternate bursts, or interleave, whichever you
prefer. Average or lowpass filter each set to a single signed value
and do the trig. Calibrate out any constant phase error.
Mathematically, this is close to the heterodyne thing you suggest -
you wind up processing nearly the same sample set in the long run -
but may be simpler to code.

The samples don't have to be exactly 90 degrees apart, just anything
sort of close and repeatable; more trig.

John

 

[john jardine]

"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.
[...]
Adam

Adam.
Damned service supplier is only showing 80% of the posts here, so missed
your reply. Saw it on Google groups but have now even lost that, so working
from memory.
Yes, "phase sensitive rectifiers" (the very soul of analogue electronics)
are same thing as the +/- 1 multipliers you drew. And indeed, your idea
works well. Had simmed a similar setup a while ago, so ran it with an equal
sig/noise reference input (only 1kc). A 500ms sampling period integrated out
to a couple % error on the ratio magnitude and angle, which is of course the
whole idea.

Don't know about you but now I've seen where the signal handling road ends,
I'm losing interest in getting there, so now looking into ways of reducing
the chip count and cost to a minimum. At the moment I'm finishing off a
voltage controlled sine wave oscillator to replace an expensive DDS
reference source. The osc' offers 0.1% thd and linear sweeps but much more
usefully, has thrown up a couple of 'what ifs' for future perusal
regards
john

 

[Adam S]

john jardine wrote:

"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

I have application where I want to determine the phase/magnitude between
two signals, each of which contains a continuous 100kHz sine wave, and
with low as 0dB S/N ratio. The frequency of the source signal will be
generated by the microcontroller.

[...]

Adam


Adam.
Damned service supplier is only showing 80% of the posts here, so missed
your reply. Saw it on Google groups but have now even lost that, so working
from memory.
Yes, "phase sensitive rectifiers" (the very soul of analogue electronics)
are same thing as the +/- 1 multipliers you drew. And indeed, your idea
works well. Had simmed a similar setup a while ago, so ran it with an equal
sig/noise reference input (only 1kc). A 500ms sampling period integrated out
to a couple % error on the ratio magnitude and angle, which is of course the
whole idea.

Don't know about you but now I've seen where the signal handling road ends,
I'm losing interest in getting there, so now looking into ways of reducing
the chip count and cost to a minimum. At the moment I'm finishing off a
voltage controlled sine wave oscillator to replace an expensive DDS
reference source. The osc' offers 0.1% thd and linear sweeps but much more
usefully, has thrown up a couple of 'what ifs' for future perusal
regards
john

Well, that makes my decision a lot easier then. The "dual channel phase
sensitive rectifier" I drew uses a quite a few parts. Although there is
nothing fancy in my design, I have a total of 26 op-amps! I
need selectable frequencies, at 100Hz, 1kHz, 10kHz or 100kHz. The
simplest method I could think of generating such signals was to convert
square waves to sine waves with low pass filtering (totaling 8 op-amps
in 2x LMV824 quad ICs). The LPF is feed by the summing junction of two
60° phase shifted square waves generated by the microcontroller. Summing
two 60° square waves cancels out 3rd, 9th, 15th,... harmonics, making it
easier on the filter specification. Simulation had showed that using the
above technique with a 2nd order 1dB ripple Chebyshev low pass, the TDH
was 0.8%, while a steeper 4th order filter resulted in only 0.03% THD.

John.L suggestion on alternating between 0 and 90° phases of the local
oscillator signal would save a bit of hardware. Its a good idea but
unfortunately it will slow response time since I now have to wait for
the low pass filter outputs to settle between switching phases.

I'm curious as to what frequency and span can you get from your voltage
controlled sine wave oscillator ?

 

[john jardine]

"Adam S" <no@body.home.com> wrote in message
news:42f4ab60$0$19001$afc38c87@news.optusnet.com.au...

john jardine wrote:
[...]
"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

Well, that makes my decision a lot easier then. The "dual channel phase
sensitive rectifier" I drew uses a quite a few parts. Although there is
nothing fancy in my design, I have a total of 26 op-amps! I
need selectable frequencies, at 100Hz, 1kHz, 10kHz or 100kHz. The
simplest method I could think of generating such signals was to convert
square waves to sine waves with low pass filtering (totaling 8 op-amps
in 2x LMV824 quad ICs). The LPF is feed by the summing junction of two
60° phase shifted square waves generated by the microcontroller. Summing
two 60° square waves cancels out 3rd, 9th, 15th,... harmonics, making it
easier on the filter specification. Simulation had showed that using the
above technique with a 2nd order 1dB ripple Chebyshev low pass, the TDH
was 0.8%, while a steeper 4th order filter resulted in only 0.03% THD.

John.L suggestion on alternating between 0 and 90° phases of the local
oscillator signal would save a bit of hardware. Its a good idea but
unfortunately it will slow response time since I now have to wait for
the low pass filter outputs to settle between switching phases.

I'm curious as to what frequency and span can you get from your voltage
controlled sine wave oscillator ?



26 opamps, not bad!. For development I throw 'em in like there's no

tomorrow. Nothing worse than late in the game having to add one or two to
cure a problem. Easy then to lose the surplus after the job has been
sorted.
Neat idea of summing 2 shifted square waves. Just been playing with it's
sim, (one ratio gave virtually no 'FFTed' 2nd, 3rd, or 4th!). It's nowadays
a pleasure using a micro, to generate precise waveforms on demand and the
way I'll also go for a fixed frequency. Just done an L.V.D.T controller for
a customer. Excitation sinewave comes from the filtered 50:50 square wave
off a CMOS gate (3rd order Cheb). Thd about .4% but more importantly (for
the LVDT), the sine amplitude is stable, as it's now locked to a DC
reference rail. Only thing to worry about is filter capacitor tempcos
shifting the response curve.

Using cheap kit, there's no way my VCSWO thing can go beyond say 50kHz
It's setup to give 20Hz to 20kHz in 2 ranges and can only cover a 30:1
frequency span on each range.
Basically I've opted for an audio sweep, as since day #1 I've found it nigh
on impossible to make a good, single frequency measurement, of something
supposedly as simple as a power transformer. Voltage control allows choice
of opting for particular spot frequencies, or a continuous vector sweep
under control of a PC say.
The VCosc' has been fun to play with and dead simple. Maybe I can put it on
ABSE while it's still in a general purpose form.
regards
john.

 

[Adam S]

john jardine wrote:

"Adam S" <no@body.home.com> wrote in message
news:42f4ab60$0$19001$afc38c87@news.optusnet.com.au...

john jardine wrote:

[...]

"Adam S" <no@body.home.com> wrote in message
news:42f1e3ee$0$25984$afc38c87@news.optusnet.com.au...

Well, that makes my decision a lot easier then. The "dual channel phase
sensitive rectifier" I drew uses a quite a few parts. Although there is
nothing fancy in my design, I have a total of 26 op-amps! I
need selectable frequencies, at 100Hz, 1kHz, 10kHz or 100kHz. The
simplest method I could think of generating such signals was to convert
square waves to sine waves with low pass filtering (totaling 8 op-amps
in 2x LMV824 quad ICs). The LPF is feed by the summing junction of two
60° phase shifted square waves generated by the microcontroller. Summing
two 60° square waves cancels out 3rd, 9th, 15th,... harmonics, making it
easier on the filter specification. Simulation had showed that using the
above technique with a 2nd order 1dB ripple Chebyshev low pass, the TDH
was 0.8%, while a steeper 4th order filter resulted in only 0.03% THD.

John.L suggestion on alternating between 0 and 90° phases of the local
oscillator signal would save a bit of hardware. Its a good idea but
unfortunately it will slow response time since I now have to wait for
the low pass filter outputs to settle between switching phases.

I'm curious as to what frequency and span can you get from your voltage
controlled sine wave oscillator ?




26 opamps, not bad!. For development I throw 'em in like there's no
tomorrow. Nothing worse than late in the game having to add one or two to
cure a problem. Easy then to lose the surplus after the job has been
sorted.
Neat idea of summing 2 shifted square waves. Just been playing with it's
sim, (one ratio gave virtually no 'FFTed' 2nd, 3rd, or 4th!).

Yes, I did the math once and it showed that it cancels out 3rd and 9th,
harmonics (plus others but I can't remember the sequence). It was only
using trigonometry identities.


It's nowadays

a pleasure using a micro, to generate precise waveforms on demand and the
way I'll also go for a fixed frequency. Just done an L.V.D.T controller for
a customer. Excitation sinewave comes from the filtered 50:50 square wave
off a CMOS gate (3rd order Cheb). Thd about .4% but more importantly (for
the LVDT), the sine amplitude is stable, as it's now locked to a DC
reference rail. Only thing to worry about is filter capacitor tempcos
shifting the response curve.

Using cheap kit, there's no way my VCSWO thing can go beyond say 50kHz
It's setup to give 20Hz to 20kHz in 2 ranges and can only cover a 30:1
frequency span on each range.
Basically I've opted for an audio sweep, as since day #1 I've found it nigh
on impossible to make a good, single frequency measurement, of something
supposedly as simple as a power transformer. Voltage control allows choice
of opting for particular spot frequencies, or a continuous vector sweep
under control of a PC say.

If its 20-20kHz and the product your making will be next to a PC then
you can do a lot with soundcard. I did some playing around with
soundcard for vector extraction of sine waves, and found them to be
quite accurate. If I remember correctly THD+N was ~0.03%, and channel
crosstalk was good. The two unknown sine waves are conditioned for <=
2.8Vpk-pk to the soundcard line inputs, and quadrature demodulation is
performed in software. I still have the C++ code somewhere you are
welcome to have. The incoming data is quadrature demodulated,

A[n] = cos(F*n)*x[n]
A[n] = sin(F*n)*x[n]
C[n] = cos(F*n)*y[n]
D[n] = sin(F*n)*y[n]

where
n = sample number 0,1,2....
F = local oscillator frequency
x[n] = left channel sample data
y[n] = right channel sample data

A[n],B[n],C[n],D[n] = complex real and imaginary components of incoming
signal. Pass these though a low pass filter and use the DC values to
compute relative phase and magnitude. The sin/cos functions were
generated using a "digital oscillator" to help with CPU loading.

The VCosc' has been fun to play with and dead simple. Maybe I can put it on
ABSE while it's still in a general purpose form.

I'd be very interesting having a look how its done. I haven't had a much
experience with electronics and the only sine wave VCO I know of is RF
LC osc. using a variac diode.
If you like yYou can mail me directly at:

a<underscore>seychell<at>yahoo,com,au


Adam