sample and hold block block AC simulations

[AG]

Is there any 'sample and hold' block in Cadence libraries, which I can
use in ac-simulations. What I am looking for is a block which outputs
the fourier-transform of the signal when the signal goes through that
sample and hold circuit with clock frequency as the input parameter to
the S&H block.

 

[Andrew Beckett]

On 04/23/12 13:02, AG wrote:

Is there any 'sample and hold' block in Cadence libraries, which I can
use in ac-simulations. What I am looking for is a block which outputs
the fourier-transform of the signal when the signal goes through that
sample and hold circuit with clock frequency as the input parameter to
the S&H block.

I think we've discussed this elsewhere, but you could use something like
the Verilog-A model of a sample hold described in
http://www.designers-guide.org/Analysis/hidden-state.pdf
and then simulate with PSS/PAC

Regards,

Andrew.