same signal for latch enable & clk input.

can we use same signal for latch enable & clk input.

like clk is a signal which is enable input of latch and also a clock
input to another flip flop?

 

[gabor]

There's no reason you can't use the same signal for latch and
clock. If you're asking if it can be synthesized, it depends on the
chip you target. For FPGA's most global clock routing works
well for both latch enable and clock, since the logic block input
is usually the same for both (at least for Xilinx parts, I'm not an
expert on others).

jitendrakumawat@gmail.com wrote:

can we use same signal for latch enable & clk input.

like clk is a signal which is enable input of latch and also a clock
input to another flip flop?

 

with xilinx the design is being synthesized......

but the results of pre synthesis simulation & post place place n route
simultion are
totally different.....?

 

[gabor]

jitendrakumawat@gmail.com wrote:

with xilinx the design is being synthesized......

but the results of pre synthesis simulation & post place place n route
simultion are
totally different.....?

Are you using a global clock net for the clock / latch gate in question?