Same procedure call in different processes ?

C

C T

Guest
I would like to write procedures that can be used in different
processes.

Here is a sample of my VHDL codes:

--------------------------------------------------------------------------------

architecture BEHAV of SBUS is

constant addr_hiZ : std_logic_vector(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant data_hiZ : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
signal read_sbus, write_sbus, rw_gsp, rw_tsp: state_type;

....

procedure readx(
signal addr : in std_logic_vector(22 downto 0);
signal data : out std_logic_vector(31 downto 0);
signal ack : in std_logic;
signal addr_o : out std_logic_vector(22 downto 0);
signal data_o : inout std_logic_vector(31 downto 0);
signal as, read, rw_done: out std_logic
) is
begin
case read_sbus is
when s0 =>
rw_done <= '0';

data_o <= data_hiZ;
addr_o <= addr_hiZ;
as <= '1' after pd;
read <= '1';
read_sbus <= s1;
....
when s5 =>
rw_done <= '1';
addr_o <= addr_hiZ;
read_sbus <= s0;
when others =>
read_sbus <= s0;
end case;
end procedure;

----similarly for procedure writex


begin --arch

GSP: process(CLK)
begin
if RESET = '0' then
....
elsif rising_edge(CLK) then
if gsp_en = '1' then
case rw_gsp is
when s0 =>
....
readx(iaddr, idata, ack, addr, data, as, read, rw_done);
....
when s1 =>
....
writex(iaddr, idata, ack, addr, data, as, read, rw_done);
....
when others =>
rw_gsp <= s0;
end case;
end if;
end if;
end process;

TSP: process(CLK)
begin
if RESET = '0' then
....
elsif rising_edge(CLK) then
if tsp_en = '1' then
case rw_tsp is
when s0 =>
....
readx(iaddr, idata, ack, addr, data, as, read, rw_done);
....
when s1 =>
....
writex(iaddr, idata, ack, addr, data, as, read, rw_done);
....
when others =>
rw_sp <= s0;
end case;
end if;
end if;
end process;

--------------------------------------------------------------------------------


I got following error messages when compiling the codes:


-- Compiling architecture behav of tsbus
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(67): Cannot
drive signal 'read_sbus' from this subprogram.

** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(111): Cannot
drive signal 'write_sbus' from this subprogram.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(172): No
feasible entries for subprogram 'readx'.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(242): No
feasible entries for subprogram 'writex'.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(394): VHDL
Compiler exiting

I tried to put signal declation for read_sbus, write_sbus, etc. in
packages but that still did not help!

How can I do it correctly then? Many thanks in advance.

Calvin
 
Have a look at
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#procedure_drivers

Egbert Molenkamp

"C T" <cathai@netzero.net> schreef in bericht
news:545465ae.0404140726.776c21b8@posting.google.com...
I would like to write procedures that can be used in different
processes.

Here is a sample of my VHDL codes:

--------------------------------------------------------------------------
------

architecture BEHAV of SBUS is

constant addr_hiZ : std_logic_vector(22 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZ";
constant data_hiZ : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

type state_type is (s0,s1,s2,s3,s4,s5,s6,s7);
signal read_sbus, write_sbus, rw_gsp, rw_tsp: state_type;

...

procedure readx(
signal addr : in std_logic_vector(22 downto 0);
signal data : out std_logic_vector(31 downto 0);
signal ack : in std_logic;
signal addr_o : out std_logic_vector(22 downto 0);
signal data_o : inout std_logic_vector(31 downto 0);
signal as, read, rw_done: out std_logic
) is
begin
case read_sbus is
when s0 =
rw_done <= '0';

data_o <= data_hiZ;
addr_o <= addr_hiZ;
as <= '1' after pd;
read <= '1';
read_sbus <= s1;
...
when s5 =
rw_done <= '1';
addr_o <= addr_hiZ;
read_sbus <= s0;
when others =
read_sbus <= s0;
end case;
end procedure;

----similarly for procedure writex


begin --arch

GSP: process(CLK)
begin
if RESET = '0' then
...
elsif rising_edge(CLK) then
if gsp_en = '1' then
case rw_gsp is
when s0 =
...
readx(iaddr, idata, ack, addr, data, as, read, rw_done);
...
when s1 =
...
writex(iaddr, idata, ack, addr, data, as, read, rw_done);
...
when others =
rw_gsp <= s0;
end case;
end if;
end if;
end process;

TSP: process(CLK)
begin
if RESET = '0' then
...
elsif rising_edge(CLK) then
if tsp_en = '1' then
case rw_tsp is
when s0 =
...
readx(iaddr, idata, ack, addr, data, as, read, rw_done);
...
when s1 =
...
writex(iaddr, idata, ack, addr, data, as, read, rw_done);
...
when others =
rw_sp <= s0;
end case;
end if;
end if;
end process;

--------------------------------------------------------------------------
------


I got following error messages when compiling the codes:


-- Compiling architecture behav of tsbus
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(67): Cannot
drive signal 'read_sbus' from this subprogram.

** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(111): Cannot
drive signal 'write_sbus' from this subprogram.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(172): No
feasible entries for subprogram 'readx'.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(242): No
feasible entries for subprogram 'writex'.
** Error: H:/Documents/Digital IO/VHDL Files/tsbus.vhd(394): VHDL
Compiler exiting

I tried to put signal declation for read_sbus, write_sbus, etc. in
packages but that still did not help!

How can I do it correctly then? Many thanks in advance.

Calvin
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top