Same bitstream files give different behavior.

[Adarsh Kumar Jain]

Hi All,
This may be a strange question ..
I program 9 Xilinx Devices with the same bitstream file.
But some of them behave differently from the others.
Can anyone give me any suggestions on why this could be happening ?
Is the problem internal to Xilinx (if i am on the edge of timing on some
signals)
or it is outside in the signals coming to them ?
Any pointers will be really appreciated,
Thanks,
Adarsh

 

[MM]

Have you simulated your design? Is it fully synchronous? What is your
external clock rate?

/Mikhail


"Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message
news:cctf2s$hd7$1@sunnews.cern.ch...

Hi All,
This may be a strange question ..
I program 9 Xilinx Devices with the same bitstream file.
But some of them behave differently from the others.
Can anyone give me any suggestions on why this could be happening ?
Is the problem internal to Xilinx (if i am on the edge of timing on some
signals)
or it is outside in the signals coming to them ?
Any pointers will be really appreciated,
Thanks,
Adarsh

 

[Rajeev]

"Adarsh Kumar Jain" <adarsh.jain@cern.ch> wrote in message news:<cctf2s$hd7$1@sunnews.cern.ch>...

Hi All,
This may be a strange question ..
I program 9 Xilinx Devices with the same bitstream file.
But some of them behave differently from the others.
Can anyone give me any suggestions on why this could be happening ?
Is the problem internal to Xilinx (if i am on the edge of timing on some
signals)
or it is outside in the signals coming to them ?
Any pointers will be really appreciated,
Thanks,
Adarsh

I had the same experience due to a bug (mine) crossing clock domains
between 1x and 2x clocks. IIRC the problem was not a source code
issue, rather a missing or incorrect timing constraint. Some devices
happened to be fast enough where the unconstrained path was OK, others
failed. This was in Altera/Quartus.

Hope this helps,
-rajeev-