Safe State Machine with Conditional Statements in default cl

Can you make a finite state machine with a default clause that has a conditional statement inside? This would be for synthesizing a "safe case" state machine with Synplify Pro.

For example:

default: begin
if (a == 1'b1) begin
next_state <= IDLE;
end
else if (b == 1'b1) begin
next_state <= READ;
end
else
next_state <= ERROR;
end
end

I have never actually done this before before and have only seen simple "default" with only a single state assignment.