Run Verilog-XL error in IC5.0

[BL]

Hi, when i verify the functionality of the schematic of using
VERILOG-XL in IC5.0, STAER interactive that shown:

WARNING : VLOGIF [BADFILE GLOBAL]
user-settable global variable : verilog SimBinary is invalid, Relative
pathnames are relative to run directory OK / CANCEL abort simulation.

Simulation option warning:
Invalid verilog executable verilog
Please check existance and/or permissions and try again. Relative
pathnames are relative to run directory.

i check the license in CIW "virtuoso schematic composer verilog
interface" is running.

Please help me to solve it.

Thank you
benny

 

[Andrew Beckett]

Do you have an LDV installation (e.g. LDV51), and have your UNIX path to
include the <ldvInstDir>/tools/bin ?

"verilog" is not contained within the IC50 hierarchy, and so you need an LDV
stream installed and in your path to be able to access it.

Regards,

Andrew.

On 20 May 2004 21:15:05 -0700, benny16@mail.hongkong.com (BL) wrote:

Hi, when i verify the functionality of the schematic of using
VERILOG-XL in IC5.0, STAER interactive that shown:

WARNING : VLOGIF [BADFILE GLOBAL]
user-settable global variable : verilog SimBinary is invalid, Relative
pathnames are relative to run directory OK / CANCEL abort simulation.

Simulation option warning:
Invalid verilog executable verilog
Please check existance and/or permissions and try again. Relative
pathnames are relative to run directory.

i check the license in CIW "virtuoso schematic composer verilog
interface" is running.

Please help me to solve it.

Thank you
benny

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[BL]

Thank you. I do not have installed LDV in linux. Despite
"verilog-XL", any other software not include in IC5.0 ?

Regards,
Benny


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<lsf7b0ht6s8iv3i65qbnpuoolr71q30lof@4ax.com>...

Do you have an LDV installation (e.g. LDV51), and have your UNIX path to
include the <ldvInstDir>/tools/bin ?

"verilog" is not contained within the IC50 hierarchy, and so you need an LDV
stream installed and in your path to be able to access it.

Regards,

Andrew.

On 20 May 2004 21:15:05 -0700, benny16@mail.hongkong.com (BL) wrote:

Hi, when i verify the functionality of the schematic of using
VERILOG-XL in IC5.0, STAER interactive that shown:

WARNING : VLOGIF [BADFILE GLOBAL]
user-settable global variable : verilog SimBinary is invalid, Relative
pathnames are relative to run directory OK / CANCEL abort simulation.

Simulation option warning:
Invalid verilog executable verilog
Please check existance and/or permissions and try again. Relative
pathnames are relative to run directory.

i check the license in CIW "virtuoso schematic composer verilog
interface" is running.

Please help me to solve it.

Thank you
benny

 

[Andrew Beckett]

Verilog hasn't been in the IC stream since IC443 (IC443 was the last version it
was still there for; it wasn't there in IC445 nor IC446).

So this is nothing new. There was this effort to split out tools into
separate streams, and to avoid duplication where possible - but that was
several releases ago now.

leapfrog is also not in IC50 because it was end of lifed some time ago.

Andrew.

On 26 May 2004 20:29:20 -0700, benny16@mail.hongkong.com (BL) wrote:

Thank you. I do not have installed LDV in linux. Despite
"verilog-XL", any other software not include in IC5.0 ?

Regards,
Benny


Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<lsf7b0ht6s8iv3i65qbnpuoolr71q30lof@4ax.com>...
Do you have an LDV installation (e.g. LDV51), and have your UNIX path to
include the <ldvInstDir>/tools/bin ?

"verilog" is not contained within the IC50 hierarchy, and so you need an LDV
stream installed and in your path to be able to access it.

Regards,

Andrew.

On 20 May 2004 21:15:05 -0700, benny16@mail.hongkong.com (BL) wrote:

Hi, when i verify the functionality of the schematic of using
VERILOG-XL in IC5.0, STAER interactive that shown:

WARNING : VLOGIF [BADFILE GLOBAL]
user-settable global variable : verilog SimBinary is invalid, Relative
pathnames are relative to run directory OK / CANCEL abort simulation.

Simulation option warning:
Invalid verilog executable verilog
Please check existance and/or permissions and try again. Relative
pathnames are relative to run directory.

i check the license in CIW "virtuoso schematic composer verilog
interface" is running.

Please help me to solve it.

Thank you
benny

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd