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David Rogoff
Guest
Hi all.
More VHDL learning curve. I'm trying to copy some SystemVerilog verification code I did a couple of years ago but I'm stuck. I want to report and/or act based on the hierarchical instance of a procedure. I thought I could use the 'instance_name attribute but that only statically determined and just tells me the package name where I defined the procedure - not what I want.
How do I extra the hierarchical path during run-time? I thought of a way to do it using generics but I'd have to rewrite dozens of nested procedures and functions to plumb a path string down. Not gonna happen.
Thanks!
David
ps - I did find some handy string manipulation in VHDL 2008 (e.g. to_string(time
). I also wrote an slv to string function that adds underscores every 4 digits to make long numbers readable. I'm working on a similar function that takes a real and outputs a string with commas every 3 digits to the left and right of the decimal point. Don't suppose someone already has this? Extra points for Euro input to swap "." and "," 
More VHDL learning curve. I'm trying to copy some SystemVerilog verification code I did a couple of years ago but I'm stuck. I want to report and/or act based on the hierarchical instance of a procedure. I thought I could use the 'instance_name attribute but that only statically determined and just tells me the package name where I defined the procedure - not what I want.
How do I extra the hierarchical path during run-time? I thought of a way to do it using generics but I'd have to rewrite dozens of nested procedures and functions to plumb a path string down. Not gonna happen.
Thanks!
David
ps - I did find some handy string manipulation in VHDL 2008 (e.g. to_string(time