rtl

[bir]

Guys

I need some help. Look at the style of the codes below.

reg a;

always @(negedge tlr, posedge tclk)
if (!tlr)
a <= 0;
else
if (read)
a <= 1;

and now look below.

always @(negedge tlr, posedge tclk)
begin
if (tlr==1'b0)
a <= 1'b0;
else
if (read==1'b1)
a <= 1'b1;
end

My questions are

1. How necessary is it to use begin and end in always block at the
start and end of an always block in a situation like this above.

2. For the the condition how is tlr == 1'b0 better than using (!tlr) or
vice versa.

3. Finally what difference does it make between
a <= 0; a<= 1'b0;

I was told that a<=0 is not a good practise?? What would an rtl
from a generic point of view look like with the above code in
considereation.

Plz help me out with solid reasons.

Thanks
Rik

 

[Michael]

1. You don't need "begin-end" if you have one statement only.
2. It is exactly the same because it is 1-bit wire. (!tlr) is just
shorter.
3. Again it is the same in this case but if for some reason you want to
expand your "a" to 2 or more bits "a<=1" will be expanded to
"a<=2'b01". I prefer to use specific description "a<=1'b1;".

But in general both descriptions of FF are equal.

 

[Michael]

1. You don't need "begin-end" if you have one statement only.
2. It is exactly the same because it is 1-bit wire. (!tlr) is just
shorter.
3. Again it is the same in this case but if for some reason you want to
expand your "a" to 2 or more bits "a<=1" will be expanded to
"a<=2'b01". I prefer to use specific description "a<=1'b1;".

But in general both descriptions of FF are equal.

 

[Utku Özcan]

1. How necessary is it to use begin and end in always block at the
start and end of an always block in a situation like this above.

begin/end pair is useful to create named blocks, which easies to debug
the design in elaboration and simulation time. I take your always block
as example:

always @(negedge tlr, posedge tclk)
begin : READ_REG_A
if (tlr==1'b0)
a <= 1'b0;
else
if (read==1'b1)
a <= 1'b1;
end

In the example above, I have named your block with "READ_REG_A".

Supposing you have named all your blocks in your design, you can do
fancy stuff thru compiletf routines of your PLI function (elaboration
time) or calltf routines of your PLI function (simulation time), in
which you can trace the blocks thru their names.

Utku.

 

It's mostly (completely?) a matter of style.

1) The begin/end is not _necessary_. But I did spend a day debugging
some code where the original author was not consistent, and because of
the lack of begin/end in some areas, an else clause was attached to the
wrong if.

2) This is typical of Verilog coders that learned VHDL first, or work
in both languages on a regular basis. There is no difference in the
operation of either, and the '=' (vhdl) vs/ '==' (verilog) will still
screw you up anyway.

3) Again, the two statements are equivalent. The person who told you
that it was "not good practice" had probably gotten burned by the
default bit-filling, and didn't enjoy it.

As long as your code is readable/maintainable by you and your teams
members, "it doesn't matter". But the grey-haired guys are usually
pretty set in their ways, and it's usually easier to go along rather
than fight them. Heck, you may even learn something from one of them.