G
George (Lingkan) Gong
Guest
Hi,
Are you working on Dynamic Partial Reconfiguration (DPR)? Are you struggling to get your DPR design working? Are you frustrated with using ChipScope?
I am a PhD student from the University of New South Wales, Australia, and I am very interested in the Partially Reconfiguration, particularly the functional verification of Partially Reconfigurable designs.
Similar to traditional static FPGA designs, DPR designs are also created by writing Verilog/VHDL code. However, the design source can not be simulated because HDL simulators do not support RTL simulation of partial reconfiguration. Traditional HDL languages assume that the design hierarchy is defined at compile-time and can not be changed in the middle of a simulation run.
I am currently working on an open source library, ReSim, for simulation-based functional verification of DPR designs. By compiling the library and your design HDL source, you can perform cycle-accurate RTL simulation of your DPR design, including the partial reconfiguration process, in HDL simulators such as ModelSim. The designer can view in the waveform window all the signal transitions during the reconfiguration process, such as the transfer of the partial bitstreams and the subsequent swapping of reconfigurable modules.
You can find my latest ReSim library on Google Code:
http://code.google.com/p/resim-simulating-partial-reconfiguration/
You are welcome to use it and I would be happy to hear from you any feedback of using the tool.
Thanks and Kind Regards,
Are you working on Dynamic Partial Reconfiguration (DPR)? Are you struggling to get your DPR design working? Are you frustrated with using ChipScope?
I am a PhD student from the University of New South Wales, Australia, and I am very interested in the Partially Reconfiguration, particularly the functional verification of Partially Reconfigurable designs.
Similar to traditional static FPGA designs, DPR designs are also created by writing Verilog/VHDL code. However, the design source can not be simulated because HDL simulators do not support RTL simulation of partial reconfiguration. Traditional HDL languages assume that the design hierarchy is defined at compile-time and can not be changed in the middle of a simulation run.
I am currently working on an open source library, ReSim, for simulation-based functional verification of DPR designs. By compiling the library and your design HDL source, you can perform cycle-accurate RTL simulation of your DPR design, including the partial reconfiguration process, in HDL simulators such as ModelSim. The designer can view in the waveform window all the signal transitions during the reconfiguration process, such as the transfer of the partial bitstreams and the subsequent swapping of reconfigurable modules.
You can find my latest ReSim library on Google Code:
http://code.google.com/p/resim-simulating-partial-reconfiguration/
You are welcome to use it and I would be happy to hear from you any feedback of using the tool.
Thanks and Kind Regards,