RTL design of Blocking ans NonBlocking

[himassk]

Hi,

Please clarify me about blocking and nonblocking statement
difference in RTL design.

CODE1:
always@(X or Y or Z)
begin
Q1 = X & Y;
Q2 = Q1 & Z;
end

CODE2:
always@(X or Y or Z)
begin
Q1 <= X & Y;
Q2 <= Q1 & Z;
end

Theoritically Q2 in CODE 2 is assigned with the previous value of
Q1&Z and Q2 in CODE 1 is assigned with the updated value of Q1&Z.

But RTL design generated (after synthesis) for both codes are
obsolutely same.
If the RTL design mapped in to core is same then how these two codes
function differently?

In simulation we can see the difference because the compiler stores
the previous value of Q1 in to temperory buffer and assigns to Q2.
But in RTL design no buffer is available, so how can the
functionality difference occurs in practicle?

Thanks in advance.

Regards,
SruthiTeja.

 

[Ralf Hildebrandt]

himassk wrote:

CODE1:
always@(X or Y or Z)
begin
Q1 = X & Y;
Q2 = Q1 & Z;
end

CODE2:
always@(X or Y or Z)
begin
Q1 <= X & Y;
Q2 <= Q1 & Z;
end

Theoritically Q2 in CODE 2 is assigned with the previous value of
Q1&Z and Q2 in CODE 1 is assigned with the updated value of Q1&Z.

Right. That's the reason why you have to add Q1 to the sensitivity list
of always statement 2.

always@(X or Y or Z or Q1)
begin
Q1 <= X & Y;
Q2 <= Q1 & Z;
end

After Q1 is modified the statement is triggered again and the new value
is assigned to Q2. This slows down simulation compared to the always
statement 1 with the non-blocking assignments, but you get the correct
behavior.

But RTL design generated (after synthesis) for both codes are
obsolutely same.

Synthesis tools do not care about sensitivity lists. => A pitfall if you
sensitivity list is incomplete as in code 2.


Do you speak VHDL? There it is much easier. Nonblocking assignments
(Verilog '=') are similar to variable assignments (VHDL ':=') and
blocking assignments (Verilog '<=') are similar to signal assignments
(VHDL '<='). If speak VHDL and if you have this in mind it is easy to
see what happens to the signals.

With a nonblocking assignment ('=') the value is stored immediately
while with a blocking assignment ('<=') the assignment is delayed and
done later. There is an event queue where all assignments, that are
delayed are stored.



Have a look at
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf#search=%22Cummings%20coding%20styles%20that%20kill%22

Ralf

 

[Paul Uiterlinden]

Ralf Hildebrandt wrote:

With a nonblocking assignment ('=') the value is stored immediately
while with a blocking assignment ('<=') the assignment is delayed
and done later. There is an event queue where all assignments, that
are delayed are stored.

AFAIK, it's the other way around: '=' is called the blocking
assignment, '<=' is called the non-blocking assignment.

--
Paul.

 

[Ralf Hildebrandt]

Paul Uiterlinden wrote:

AFAIK, it's the other way around: '=' is called the blocking
assignment, '<=' is called the non-blocking assignment.

Yes - sorry - my fault. Sometimes I forget to turn on my brain.

Ralf

 

[Muks]

Shruthi,

You can go thru paper mentioned by Ralf. It has every explanation to
your doubt.

Synthesis wise there is no difference in both the examples, Synthesis
will generate same hardware. Simulation wise you will not see the same
result for coded both the examples. Your always block with NBA
(nonblocking assignment) is bad simulation design.

I think you want to write combo logic in always block. Use blocking
assignments for combinational logic.

More things will be clear if you go thru that paper by cliffc.

Thanks
Mukesh

Paul Uiterlinden wrote:

Ralf Hildebrandt wrote:

With a nonblocking assignment ('=') the value is stored immediately
while with a blocking assignment ('<=') the assignment is delayed
and done later. There is an event queue where all assignments, that
are delayed are stored.

AFAIK, it's the other way around: '=' is called the blocking
assignment, '<=' is called the non-blocking assignment.

--
Paul.