K
Konx
Guest
Hi everyone.
I'm using RTL Compiler to synthesize some Verilog blocks. I can run RC without problems for a small block (I've tried a shift register).
The problem is the following:
I have a big block called Pixel. This block has a schematic view and is made of many sub-block: some of them are verilog others are schematic (they don't have a verilog description, they are custom made). In the Pixel-schematic every block is instantiated using its symbol view and connected with nets.
What I want to do is to say to the RTL compiler that it has to take all the blocks in the Pixel that have a Verilog description and synthesize them.
Is it possible? or is it necessary that I describe the connectivity of the verilog blocks in a top-level verilog and then synthesize it directly?
I hope the problem it is clear,
thanks for any helps,
Konx
I'm using RTL Compiler to synthesize some Verilog blocks. I can run RC without problems for a small block (I've tried a shift register).
The problem is the following:
I have a big block called Pixel. This block has a schematic view and is made of many sub-block: some of them are verilog others are schematic (they don't have a verilog description, they are custom made). In the Pixel-schematic every block is instantiated using its symbol view and connected with nets.
What I want to do is to say to the RTL compiler that it has to take all the blocks in the Pixel that have a Verilog description and synthesize them.
Is it possible? or is it necessary that I describe the connectivity of the verilog blocks in a top-level verilog and then synthesize it directly?
I hope the problem it is clear,
thanks for any helps,
Konx