RTL code with synthesis mismatch and large runtime

[Gab]

Hi,

I'm working on a rtl block,
highly configurable through parameters,
at first sight i did not have trouble meeting timing
constraints. But i paid more attention and i tried equivalence
checking between netlist and rtl !!! actually i understood
that synthesis
tool did not infer the right logic at all ! (a lot of mismatch)
Moreover the synthesis runtime is very large ...
see rtl below (simplified) as an example... of course enable condition
may be a "bit more" complicated.

I would like to know if one of you has already experienced
problems with this kind of rtl "structure"
.... for info i use it a LOT in my block
FOCUS your attention on how the state_bank vector is generated.
(state_bank <= state_bank_combo)


thanks,
Gab

RTL code below

module core(
clock,
resetn,
enable,
data_in1,
data_in2,
data_in3,
data_out
);

parameter BANK_SIZE = 4;
parameter VECTOR_SIZE = 3;
parameter VECTOR_BANK_SIZE =
VECTOR_SIZE * BANK_SIZE;

input clock;
input resetn;
input [BANK_SIZE-1:0] enable;
input [VECTOR_SIZE-1:0] data_in1;
input [VECTOR_SIZE-1:0] data_in2;
input [VECTOR_SIZE-1:0] data_in3;
output [VECTOR_BANK_SIZE-1:0] data_out;

integer i;
reg [VECTOR_SIZE-1:0] data_in_combo;
reg [VECTOR_BANK_SIZE-1:0] state_bank;
reg [VECTOR_BANK_SIZE-1:0] state_bank_combo;
reg [VECTOR_SIZE-1:0] state_slice;

assign data_out = state_bank;

always @(posedge clock or negedge resetn)
if (!resetn)
state_bank <= {VECTOR_BANK_SIZE{1'b0}};
else begin
state_bank_combo = 0;
for (i=0;i<BANK_SIZE;i=i+1)
begin
if (&data_in1)
data_in_combo = data_in2;
else if (&data_in2)
data_in_combo = data_in3;
else if (&data_in3)
data_in_combo = data_in1;
else
data_in_combo = {VECTOR_SIZE{1'b0}};

if (enable)
state_slice = data_in_combo;
else
state_slice = state_bank >> (VECTOR_SIZE*i);
state_bank_combo = (state_slice << (VECTOR_SIZE*i)) |
state_bank_combo;
end
state_bank <= state_bank_combo;
end


endmodule

 

[Swapnajit Mittra]

It is difficult to predict what's wrong without the actual
code, but try the following which separates between
blocking and non-blocking assignment regions. There is also
scope of improvement in the areas of shift operators.

- Swapnajit
_____________________________________________________________
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
Project VeriPage: http://www.project-veripage.com
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module core(
clock,
resetn,
enable,
data_in1,
data_in2,
data_in3,
data_out
);

parameter BANK_SIZE = 4;
parameter VECTOR_SIZE = 3;
parameter VECTOR_BANK_SIZE = VECTOR_SIZE * BANK_SIZE;

input clock;
input resetn;
input [BANK_SIZE-1:0] enable;
input [VECTOR_SIZE-1:0] data_in1;
input [VECTOR_SIZE-1:0] data_in2;
input [VECTOR_SIZE-1:0] data_in3;
output [VECTOR_BANK_SIZE-1:0] data_out;

integer i;
reg [VECTOR_SIZE-1:0] data_in_combo;
reg [VECTOR_BANK_SIZE-1:0] state_bank;
reg [VECTOR_BANK_SIZE-1:0] state_bank_combo;
reg [VECTOR_SIZE-1:0] state_slice;

assign data_out = state_bank;

always @(posedge clock or negedge resetn) begin
if (!resetn)
state_bank <= {VECTOR_BANK_SIZE{1'b0}};
else
state_bank <= state_bank_combo;
end

always @* begin
state_bank_combo = 0;
if (&data_in1)
data_in_combo = data_in2;
else if (&data_in2)
data_in_combo = data_in3;
else if (&data_in3)
data_in_combo = data_in1;
else
data_in_combo = {VECTOR_SIZE{1'b0}};

for (i=0;i<BANK_SIZE;i=i+1) begin
if (enable)
state_slice = data_in_combo;
else
state_slice = state_bank >> (VECTOR_SIZE*i);

state_bank_combo =
(state_slice << (VECTOR_SIZE*i)) | state_bank_combo;
end
end
endmodule