RTL behavioural newby questions

[Larty]

I am learning Verilog, and I am confused by what the difference is
between RTL and behavioural code. I have been going through the book
by Samir Palnitkar (Verilog HDL), but this does not adequately explain
the differences. Can anyone shed some light on the above, and provide
some clear examples?

Thanks,
Larty.

 

[Carson Pun]

Larty wrote:

I am learning Verilog, and I am confused by what the difference is
between RTL and behavioural code. I have been going through the book
by Samir Palnitkar (Verilog HDL), but this does not adequately explain
the differences. Can anyone shed some light on the above, and provide
some clear examples?

Thanks,
Larty.

The difference between RTL and behvorial code is the former can be
"synthesized" whereas the later cannot.

RTL code can be synthesized meaning, it can be implemented on the chip.
behavorial code (e.g. a testbench) is not synthesizable, meaning it
cannot be implemented. (i.e. you are not supposed to put that part of
the code into say dc_shell, and expect it will give u a netlist.)