RS232

[Luiz Gustavo]

I have this code to send a byte for the pc:

module async_transmitter(clk, TxD_start, TxD, TxD_busy);
input clk, TxD_start;
reg [7:0] TxD_data;
output TxD, TxD_busy;

parameter ClkFrequency = 50000000; // 50MHz
parameter Baud = 115200;
parameter RegisterInputData = 1; // in RegisterInputData mode, the
input doesn't have to stay valid while the character is been
transmitted

// Baud generator
parameter BaudGeneratorAccWidth = 16;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
`ifdef DEBUG
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = 17'h10000;
`else
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc =
((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/
(ClkFrequency>>4);
`endif

wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
wire TxD_busy;
always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <=
BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;


//registradores

reg [7:0] a ;
reg [55:0] temp;
// Transmitter state machine
reg [3:0] state;
wire TxD_ready = (state==0);
assign TxD_busy = ~TxD_ready;

reg [7:0] TxD_dataReg;
always @(posedge clk) if(TxD_ready & TxD_start) TxD_dataReg <=
TxD_data;
wire [7:0] TxD_dataD = RegisterInputData ? TxD_dataReg : TxD_data;

always @(posedge clk)
TxD_data <= 8'b10101101;


always @(posedge clk)
case(state)
4'b0000: if(TxD_start) state <= 4'b0001;
4'b0001: if(BaudTick) state <= 4'b0100;
4'b0100: if(BaudTick) state <= 4'b1000; // start
4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
4'b1111: if(BaudTick) state <= 4'b0010; // bit 7
4'b0010: if(BaudTick) state <= 4'b0011; // stop1
4'b0011: if(BaudTick) state <= 4'b0000; // stop2
default: if(BaudTick) state <= 4'b0000;
endcase

// Output mux
reg muxbit;
always @(state[2:0])
case(state[2:0])
3'd0: muxbit <= TxD_dataD[0];
3'd1: muxbit <= TxD_dataD[1];
3'd2: muxbit <= TxD_dataD[2];
3'd3: muxbit <= TxD_dataD[3];
3'd4: muxbit <= TxD_dataD[4];
3'd5: muxbit <= TxD_dataD[5];
3'd6: muxbit <= TxD_dataD[6];
3'd7: muxbit <= TxD_dataD[7];
endcase

// Put together the start, data and stop bits
reg TxD;
always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); //
register the output to make it glitch free

endmodule

How can I send other bytes, for other registers, or more than one byte
of a bigger register?

 

[John_H]

"Luiz Gustavo" <luizvaleee@gmail.com> wrote in message
news:1183039829.540716.253030@w5g2000hsg.googlegroups.com...

I have this code to send a byte for the pc:

geeze - snip

How can I send other bytes, for other registers, or more than one byte
of a bigger register?

When you're done transmitting one byte, load the next byte into a transmit
shift register. Which bytes and which order is up to you for your system
design.

Your question is *so* basic that I'm lost as to where you're coming from -
are you in an intro to Verilog class? Picking up hardware design on your
own?

 

[Luiz Gustavo]

On Jun 28, 12:52 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

"Luiz Gustavo" <luizval...@gmail.com> wrote in message

news:1183039829.540716.253030@w5g2000hsg.googlegroups.com...

I have this code to send a byte for the pc:

geeze - snip

How can I send other bytes, for other registers, or more than one byte
of a bigger register?

When you're done transmitting one byte, load the next byte into a transmit
shift register. Which bytes and which order is up to you for your system
design.

Your question is *so* basic that I'm lost as to where you're coming from -
are you in an intro to Verilog class? Picking up hardware design on your
own?

I'm new with hardware projects... I am trying to read a lot of
registers with the rs232, and I have difficulty with this... My doubt
is with the clock, I have a lot of doubt to division the activities
for each pulse of clock. For example. I have that something occurs now
with a pulse of clock, but other not. And the two are into in a always
statement.
My english is not so good too, sorry...

 

[Mike Treseler]

Luiz Gustavo wrote:

I'm new with hardware projects... I am trying to read a lot of
registers with the rs232, and I have difficulty with this... My doubt
is with the clock, I have a lot of doubt to division the activities
for each pulse of clock. For example. I have that something occurs now
with a pulse of clock, but other not. And the two are into in a always
statement.

Hardware description reminds me of writing
interrupt routines for a CPU:

We have an event!
It's a rising clock edge!
What should we do?

The answer is to update all the register values
based on their present values and those of the
input ports. It doesn't matter if the registers
are synchronizers, states, counts or shifts.
They all have to be checked and updated every
clock -- even if the updated value is the same as
the present value.

I like to do this in one block with a long string
of IF and CASE statements. Others prefer several
parallel blocks wired together.

I have a uart reference design, but it is in vhdl.
I intent to translate it to verilog sometime this summer.

My english is not so good too, sorry...

My verilog is not so good either

-- Mike Treseler

 

[John_H]

"Luiz Gustavo" <luizvaleee@gmail.com> wrote in message
news:1183401538.850504.239050@c77g2000hse.googlegroups.com...

I'm new with hardware projects... I am trying to read a lot of
registers with the rs232, and I have difficulty with this... My doubt
is with the clock, I have a lot of doubt to division the activities
for each pulse of clock. For example. I have that something occurs now
with a pulse of clock, but other not. And the two are into in a always
statement.
My english is not so good too, sorry...

For RS232 communication with your hardware, you might do better to think of
different layers of abstraction.

The RS232 baud generator comes from your high speed system clock.

The bits are generated from the baud generator, typically at a 16x scale
(since that's how UARTs were designed way back when).

Each byte transferred is composed of start and stop bits along with the
pertinent data and optional parity.

Each message on the RS232 link is composed of several bytes.


You can create your own message formats to request or send data. The
(dis)assembly and communication of these messages percolates down to a level
where the detection of a complete valid message con trigger an event: when
the last byte saying "return my register value at this address" is received
and interpreted, the register value can be read and the return message
delivered.

If you align the flow of your design with the abstract events gated by an
"event detected" signal, you can process that event at system clock speeds
until you hand back off to the abstract message into the UART transmitter.

Everything can happen "at once" in an FPGA only to the extent that things
*can* be parallel. There are some things that still must be done serially
as you can note if you break down each process within the UART; bits have to
come together to define a byte based on a specified baud rate. Making the
switch to thinking of what processes can be paralleled with others might be
a large step from the software mindset but once you break down a few
processes into their serial chunks and see how they interrelate you should
be able to work better with hardware.