rs flip flop of nor gates.

I have a small question about standard rs flip flops.

If both inputs (set and reset) are 1, the latch is unstable.
What if both inputs are 0? with vhdl i get alternating results, both
outputs ( q and qnot)0, then both 1, etc.

how is this possible and what does this really mean? Could such thing
occur in real life using real components?

Hraggie.!

 

[krby_xtrm]

yeah it's possible in real components, but notice that "component" gets
larger that means your vhdl ff is not a single ff anymore... something
like that.

krby_xtrm

MadMaxRules@gmail.com wrote:

I have a small question about standard rs flip flops.

If both inputs (set and reset) are 1, the latch is unstable.
What if both inputs are 0? with vhdl i get alternating results, both
outputs ( q and qnot)0, then both 1, etc.

how is this possible and what does this really mean? Could such thing
occur in real life using real components?

Hraggie.!