Round-robin priority encoder

[Pasacco]

Dear

I am having problem to implement "circular round-robin" priority
encoder.

My goal is to implement using "generic" number of ports.

I tried to use two "for" loops.

Problem was that the index is not always increasing.

It seems that it is not possible to implement using generic.
If anyone has this experience, please let me know.

Manual implementation is below:
--------------------------------------------------------
-- 4-port circular round-robin
-- priority encoder
-- current : current pointer
-- req : request
-- next : next pointer
--------------------------------------------------------
process(current,req)
begin
case current is
when 0=>
if req(1)='1' then next<=1;
elsif req(2)='1' then next<=2;
elsif req(3)='1' then next<=3;
else next<=0;
end if;
when 1=>
if req(2)='1' then next<=2;
elsif req(3)='1' then next<=3;
elsif req(0)='1' then next<=0;
else next<=1;
end if;
when 2=>
elsif req(3)='1' then next<=3;
elsif req(0)='1' then next<=0;
elsif req(1)='1' then next<=1;
else next<=2;
end if;
when 3=>
if req(0)='1' then next<=0;
elsif req(1)='1' then next<=1;
elsif req(2)='1' then next<=2;
else next<=3;
end if;
end case;
end process;

 

[Jonathan Bromley]

On Thu, 3 Jul 2008 01:56:44 -0700 (PDT), Pasacco wrote:

Dear

I am having problem to implement "circular round-robin" priority
encoder.

My goal is to implement using "generic" number of ports.
I tried to use two "for" loops.
Problem was that the index is not always increasing.

It's probably best to normalise the index range internally
to your design. This really stupid little example should
show what I mean:

entity multi_bit_inverter is
port (A: in std_logic_vector;
Y: out std_logic_vector);
end;

architecture RTL of multi_bit_inverter is
begin

-- Export the blame if someone connected
-- inappropriate signals to this entity
assert A'length = Y'length
report "Instantiated port widths do not match"
severity FAILURE;

process (A)
variable normalised_A: std_logic_vector(A'length-1 downto 0);
variable normalised_Y: std_logic_vector(A'length-1 downto 0);
begin
normalised_A := A; -- this fixes any index direction problems.
-- Do the real work on your normalised versions:
for i in normalised_A'range loop
-- No problem with subscript directions now.
normalised_Y(i) := not normalised_A(i);
end loop;
-- Patch-up the array direction again to match the o/p port:
Y <= normalised_Y; -- again, fix-up index direction trouble.
end process;

end;

hth
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Pasacco wrote:

It is not quite clear what normalized index means

See Jonathan's variable declarations.
It means fix the vector dimensions
and direction to (A'length-1 downto 0).

If you have some idea, please let me know -:

I would consider using numeric_std.unsigned type
and the numeric_std.rotate_left function.
Related example:
http://mysite.verizon.net/miketreseler/sync_template.vhd
Good luck.

-- Mike Treseler

 

[Pasacco]

It is not quite clear what normalized index means and how to use.

In this example of priority encoder,

input :
current: integer range 0 to 3;
req: array(0 to 3) of std_logic;

output:
nxt: integer range 0 to 3;

If you have some idea, please let me know -: