round robin arbiter

Guest
can anybody explain the verilog model of round robin arbiter given as
an example in asic-world.com
 
can anybody explain the verilog model of round robin arbiter given as
an example in asic-world.com
See
http://groups.google.at/group/comp.lang.verilog/browse_thread/thread/2fea6771dd289302/42965bcea696ff15?hl=de#42965bcea696ff15

hth Günther
 

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